Table 10-4.
7
-
IPH Register
IPH - Interrupt Priority High Register (B7h)
6
5
4
3
-
PT2H
PSH
PT1H
2
PX1H
1
PT0H
Bit
Bit
Number Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 overflow interrupt Priority High bit
PT2H PT2 Priority Level
5
PT2H
0
0
0
Lowest
1
1
0
1
1
Highest
Serial port Priority High bit
PSH PS Priority Level
4
PSH
0
0
0
Lowest
1
1
0
1
1
Highest
Timer 1 overflow interrupt Priority High bit
PT1H PT1 Priority Level
3
PT1H
0
0
0
Lowest
1
1
0
1
1
Highest
External interrupt 1 Priority High bit
PX1H PX1 Priority Level
2
PX1H
0
0
0
Lowest
1
1
0
1
1
Highest
Timer 0 overflow interrupt Priority High bit
PT0H PT0 Priority Level
1
PT0H
0
0
0
Lowest
1
1
0
1
1
Highest
External interrupt 0 Priority High bit
PX0H PX0 Priority Level
0
PX0H
0
0
0
Lowest
1
1
0
1
1
Highest
Reset Value = XX00 0000b
Not bit addressable
0
PX0H
28 AT/TS8xC54/8X2
4431E–8051–04/06