80C54 Ver la hoja de datos (PDF) - Atmel Corporation

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80C54

8-bit CMOS Microcontroller 16/32 Kbytes ROM/OTP

Atmel Corporation 

If two interrupt requests of different priority levels are received simultaneously, the request of

higher priority level is serviced. If interrupt requests of the same priority level are received simul-

taneously, an internal polling sequence determines which request is serviced. Thus within each

priority level there is a second priority structure determined by the polling sequence.

Table 10-2. IE Register

IE - Interrupt Enable Register (A8h)

7

6

5

4

3

2

1

0

EA

-

ET2

ES

ET1

EX1

ET0

EX0

Bit

Bit

Number Mnemonic

Description

Enable All interrupt bit

Clear to disable all interrupts.

7

EA

Set to enable all interrupts.

If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its

own interrupt enable bit.

6

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Enable bit

5

ET2 Clear to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

Serial port Enable bit

4

ES

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

3

ET1 Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

External interrupt 1 Enable bit

2

EX1 Clear to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

1

ET0 Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

0

EX0 Clear to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0X00 0000b

Bit addressable

26 AT/TS8xC54/8X2

4431E–8051–04/06

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