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80C54 Ver la hoja de datos (PDF) - Atmel Corporation

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80C54 Datasheet PDF : 62 Pages
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AT/TS8xC54/8X2
10. Interrupt System
The TS80C54/58X2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown
in Figure 10-1.
Figure 10-1. Interrupt Control System
INT0
TF0
INT1
TF1
RI
TI
TF2
EXF2
IPH, IP
3
IE0
0
3
0
3
IE1
0
3
0
3
0
3
0
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
Individual Enable
Global Disable
Low priority
interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (See Table 10-2.). This register also contains a global disable bit,
which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Pri-
ority High register (See Table 10-4.). shows the bit values and priority levels associated with
each combination.
Table 10-1. Priority Level Bit Values
IPH.x
0
0
1
1
IP.x
Interrupt Level Priority
0
0 (Lowest)
1
1
0
2
1
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
25
4431E–8051–04/06

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