AD9250(Rev0) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD9250
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD9250 Datasheet PDF : 44 Pages
| |||
AD9250
Check FCHK, Checksum of JESD204B Interface Parameters
The JESD204B parameters can be verified through the checksum
value [FCHK] of the JESD204B interface parameters. Each lane has
a FCHK value associated with it. The FCHK value is transmitted
during the ILAS second multiframe and can be read from the
internal registers.
The checksum value is the modulo 256 sum of the parameters
listed in the No. column of Table 12. The checksum is calculated
by adding the parameter fields before they are packed into the
octets shown in Table 12.
The FCHK for the lane configuration for data coming out of
Lane 0 can be read from Register 0x79. Similarly, the FCHK for
the lane configuration for data coming out of Lane 1 can be read
from Register 0x7A.
Table 12. JESD204B Configuration Table Used in ILAS and
CHKSUM Calculation
Bit 7
Bit 0
No. (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB)
0
DID[7:0]
1
BID[3:0]
2
LID[4:0]
3
SCR
L[4:0]
4
F[7:0]
5
K[4:0]
6
M[7:0]
7
CS[1:0]
N[4:0]
8
SUBCLASS[2:0]
N’[4:0]
9
JESDV[2:0]
S[4:0]
10
CF[4:0]
Data Sheet
Additional Digital Output Configuration Options
Other data format controls include the following:
• Invert polarity of serial output data: Register 0x60, Bit[1]
• ADC data format (offset binary or twos complement):
Register 0x14, Bits[1:0]
• Options for interpreting single on SYSREF± and SYNCINB±:
Register 0x3A
• Option to remap converter and lane assignments, Register 0x82
and Register 0x83. See Figure 50 for simplified block diagram.
Re-Enable Lanes After Configuration
After modifying the JESD204B link parameters, enable the link so
that the synchronization process can begin. This is accomplished
by writing Logic 0 to Register 0x5F, Bit[0].
CONVERTER A
INPUT
CONVERTER A
SAMPLE
CONVERTER A
AD9250 DUAL ADC
A
PRIMARY CONVERTER
INPUT [0]
PRIMARY LANE
OUTPUT [0]
LANE 0
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
SECONDARY CONVERTER
B
INPUT [1]
SECONDARY LANE
OUTPUT [1]
LANE 1
SERDOUT0
CONVERTER B
INPUT
CONVERTER B
CONVERTER B
SAMPLE
A
SECONDARY CONVERTER
INPUT [1]
SECONDARY LANE
OUTPUT [1]
LANE 1
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
PRIMARY CONVERTER
B
INPUT [0]
PRIMARY LANE
OUTPUT [0]
LANE 0
LANE MUX
(SPI REGISTER
MAPPING: 0x82,0x83)
SERDOUT1
SYSREF
SYNCINB
Figure 50. AD9250 Transmit Link Simplified Block Diagram
Rev. 0 | Page 26 of 44
Share Link: