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AD9250
(Rev.:Rev0)

14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter

Analog Devices 

Data Sheet

AD9250

DIGITAL OUTPUTS

JESD204B Transmit Top Level Description

The AD9250 digital output uses the JEDEC Standard No.

JESD204B, Serial Interface for Data Converters. JESD204B is a

protocol to link the AD9250 to a digital processing device over a

serial interface of up to 5 Gbps link speeds (3.5 Gbps, 14-bit

ADC data rate). The benefits of the JESD204B interface include

a reduction in required board area for data interface routing

and the enabling of smaller packages for converter and logic

devices. The AD9250 supports single or dual lane interfaces.

JESD204B Overview

The JESD204B data transmit block assembles the parallel data from

the ADC into frames and uses 8b/10b encoding as well as optional

scrambling to form serial output data. Lane synchronization is

supported using special characters during the initial establishment

of the link, and additional synchronization is embedded in the

data stream thereafter. A matching external receiver is required

to lock onto the serial data stream and recover the data and clock.

For additional details on the JESD204B interface, refer to the

JESD204B standard.

The AD9250 JESD204B transmit block maps the output of the

two ADCs over a link. A link can be configured to use either

single or dual serial differential outputs that are called lanes.

The JESD204B specification refers to a number of parameters to

define the link, and these parameters must match between the

JESD204B transmitter (AD9250 output) and receiver.

The JESD204B link is described according to the following

parameters:

Figure 50 shows a simplified block diagram of the AD9250

JESD204B link. By default, the AD9250 is configured to use

two converters and two lanes. Converter A data is output to

SERDOUT0+/SERDOUT0−, and Converter B is output to

SERDOUT1+/SERDOUT1−. The AD9250 allows for other

configurations such as combining the outputs of both converters

onto a single lane or changing the mapping of the A and B

digital output paths. These modes are setup through a quick

configuration register in the SPI register map, along with

additional customizable options.

By default in the AD9250, the 14-bit converter word from each

converter is broken into two octets (8 bits of data). Bit 0 (MSB)

through Bit 7 are in the first octet. The second octet contains

Bit 8 through Bit 13 (LSB) and two tail bits. The tail bits can be

configured as zeros, pseudo-random number sequence or control

bits indicating overrange, underrange, or valid data conditions.

The two resulting octets can be scrambled. Scrambling is

optional; however, it is available to avoid spectral peaks when

transmitting similar digital data patterns. The scrambler uses a

self synchronizing, polynomial-based algorithm defined by the

equation 1 + x14 + x15. The descrambler in the receiver should be

a self-synchronizing version of the scrambler polynomial.

The two octets are then encoded with an 8b/10b encoder. The

8b/10b encoder works by taking eight bits of data (an octet) and

encoding them into a 10-bit symbol. Figure 51 shows how the

14-bit data is taken from the ADC, the tail bits are added, the two

octets are scrambled, and how the octets are encoded into two

10-bit symbols. Figure 51 illustrates the default data format.

• S = samples transmitted/single converter/frame cycle

(AD9250 value = 1)

• M = number of converters/converter device

At the data link layer, in addition to the 8b/10b encoding, the

character replacement is used to allow the receiver to monitor

frame alignment. The character replacement process occurs on

(AD9250 value = 2 by default, or can be set to 1)

the frame and multiframe boundaries, and implementation

• L = number of lanes/converter device

depends on which boundary is occurring, and if scrambling is

(AD9250 value = 1 or 2)

enabled.

• N = converter resolution (AD9250 value = 14)

• N’ = total number of bits per sample (AD9250 value = 16)

• CF = number of control words/frame clock cycle/converter

device (AD9250 value = 0)

If scrambling is disabled, the following applies. If the last scrambled

octet of the last frame of the multiframe equals the last octet of

the previous frame, the transmitter replaces the last octet with

the control character /A/ = /K28.3/. On other frames within the

• CS = number of control bits/conversion sample

multiframe, if the last octet in the frame equals the last octet of

(configurable on the AD9250 up to 2 bits)

the previous frame, the transmitter replaces the last octet with

• K = number of frames per multiframe (configurable on

the control character /F/= /K28.7/.

the AD9250)

• HD = high density mode (AD9250 value = 0)

• F = octets/frame (AD9250 value = 2 or 4, dependent upon

L = 2 or 1)

• C = control bit (overrange, overflow, underflow; available

If scrambling is enabled, the following applies. If the last octet of

the last frame of the multiframe equals 0x7C, the transmitter

replaces the last octet with the control character /A/ = /K28.3/.

On other frames within the multiframe, if the last octet equals

0xFC, the transmitter replaces the last octet with the control

on the AD9250)

character /F/ = /K28.7/.

• T = tail bit (available on the AD9250)

• SCR = scrambler enable/disable (configurable on the AD9250)

• FCHK = checksum for the JESD204B parameters

(automatically calculated and stored in register map)

Refer to JEDEC Standard No. 204B-July 2011 for additional

information about the JESD204B interface. Section 5.1 covers

the transport layer and data format details and Section 5.2

covers scrambling and descrambling.

Rev. 0 | Page 23 of 44

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