A40MX02 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Fabricante

A40MX02

40MX and 42MX FPGA Families

Unspecified 

40MX and 42MX FPGA Families

Array

Clocks

Input Delays

I/O Module

tINYL=0.8 ns

Internal Delays

tIRD1=2.0 ns†

Predicted

Routing

Delays

Output Delays

I/O Module

DQ

G

Combinatorial

Logic Module

tPD=1.2 ns

ttRRDD12==01..79

ns

ns

tRD4=1.4 ns

tRD8=2.3 ns

tDLH=2.5 ns

I/O Module

ttIINNHSU==00.0.3nns s

tINGL=1.3 ns

Sequential

Logic Module

tDLH=2.5 ns

Combin

-atoria l

Logic

include

DQ

DQ

tRD1=0.70 ns

tENHZ=4.9 ns

G

tCKH=2.70 ns

FMAX=296 MHz

FO = 32

ttSHUDD==00.0.30

ns

ns

tCO=1.3 ns

tLCO=5.2 ns (light loads, pad-to-pad)

tttOOGLUUHTT=HS2U=.=060.0n.30s

ns

ns

Notes: * Values are shown for A42MX36 ‘–3’ at 5.0V worst-case commercial conditions.

** Load-dependent

Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)

Input Delays

I/O Module

tINPY=1.0ns tIRD1=2.0ns

DQ

G

tINSU=0.5ns

tINH=0.0ns

tINGO=1.4ns

Array

Clocks

FMAX =167 MHz

WD [7:0]

WRAD [5:0]

BLKEN

WEN

WCLK

tADSU=1.6ns

tADH=0.0ns

tWENSU=2.7ns

tBENS=2.8ns

RD [7:0]

RDAD [5:0]

REN

RCLK

tADSU=1.6ns

tADH=0.0ns

tRENSU=0.6ns

tRCO=3.4ns

Predicted

Routing

Delays

tRD1=0.9ns

Note: *Values are shown for A42MX36 ‘–3 at 5.0V worst-case commercial conditions.

Figure 1-20 • 42MX Timing Model (SRAM Functions)

I/O Module

tDLH=2.6ns

DQ

G

tGHL=2.9ns

tLSU=0.5ns

tLH=0.0ns

1-24

v6.0

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