A40MX02 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Fabricante

A40MX02

40MX and 42MX FPGA Families

Unspecified 

Parameter Measurement

40MX and 42MX FPGA Families

E

D TRIBUFF

PAD To AC test loads (shown below)

In 50% 50%

PAD

VOH

1.5V

1.5V

VOL

tDLH

tDHL

Figure 1-21 • Output Buffer Delays

E

PAD

50% 50%

VCCI

1.5V

VOL

10%

tENZL tENLZ

E 50% 50%

VOH

PAD

1.5V

GND

90%

tENZH tENHZ

Load 1

(Used to measure propagation delay)

To the output under test

35 pF

Load 2

(Used to measure rising/falling edges)

VC CI

GND

To the output under test

R

R

to

to

VGCNCDI ffoorrttPPLHZZ/t/PtPZZLH

R=1k Ω

35 pF

Figure 1-22 • AC Test Loads

PAD

INBUF Y

3V

PAD 1.5V 1.5V 0V

Y

GND

VCCI

50%

50%

tINYH

tINYL

Figure 1-23 • Input Buffer Delays

S

A

Y

B

S, A or B 50% 50%

Y

50%

50%

tPLH

PHL

Y

50%

tPHL

50%

tPLH

Figure 1-24 • Module Delays

v6.0

1-25

Share Link: