A40MX02 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Fabricante

A40MX02

40MX and 42MX FPGA Families

Unspecified 

Timing Models

40MX and 42MX FPGA Families

Input Delay

Predicted

Internal Delays Routing

Delays

I/O Module

tINYL=0.62 ns tIRD2=2.59 ns

Output Delay

I/O Module

Logic Module

tttIIIRRRDDD148===235...067943

ns

ns

ns

ttPCDO==11..2244nnss

ttttRRRRDDDD1248====1124....28398033

ns

ns

ns

ns

tDLH=3.32 ns

tENHZ=7.92 ns

Array

Clock

tCKH=4.55 ns

FO=128

FMAX=180 MHz

Note:

* Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.

Figure 1-17 • 40MX Timing Model*

Array

Clocks

Input Delays

I/O Module

tINYL=0.8 ns

Internal Delays

tIRD1=2.0 ns†

Predicted

Routing

Delays

Output Delays

I/O Module

DQ

G

ttIINNHSU==00.0.3nns s

tINGL=1.3 ns

Combinatorial

Logic Module

tPD=1.2 ns

tRD1=0.7 ns

ttRRDD24==11..94

ns

ns

tRD8=2.3 ns

Sequential

Logic Module

tDLH=2.5 ns

I/O Module

tDLH=2.5 ns

Combin

-atoria l

Logic

include

DQ

DQ

tRD1=0.70 ns

tENHZ=4.9 ns

G

tCKH=2.70 ns

FMAX=296 MHz

FO = 32

ttSHUDD==00.0.30

ns

ns

tCO=1.3 ns

tLCO=5.2 ns (light loads, pad-to-pad)

tOUTH=0.00 ns

ttOGLUHT=S2U.=60n.3s ns

Notes: *Values are shown for A42MX09 ‘–3’ at 5.0V worst-case commercial conditions.

† Input module predicted routing delay.

Figure 1-18 • 42MX Timing Model*

v6.0

1-23

Share Link: