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PF28F1602C3TD70

Intel® Advanced+ Boot Block Flash Memory (C3)

Intel 

C3 SCSP Flash Memory

Bit Number

NOTES:

SR.7 WRITE STATE MACHINE STATUS

1 = Ready (WSMS)

0 = Busy

Check Write State Machine bit first to determine Word Program or

Block Erase completion, before checking Program or Erase Status

bits.

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase In Progress/Completed

When Erase Suspend is issued, WSM halts execution and sets

both WSMS and ESS bits to 1. ESS bit remains set to 1 until an

Erase Resume command is issued.

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erase

0 = Successful Block Erase

When this bit is set to 1, WSM has applied the max. number of

erase pulses and is still unable to verify successful block erasure.

SR.4 = PROGRAM STATUS (PS)

1 = Error in Programming

0 = Successful Programming

When this bit is set to 1, WSM has attempted but failed to program

a word/byte.

SR.3 = F-VPP STATUS (VPPS)

1 = F-VPP Low Detect, Operation Abort

0 = F-VPP OK

SR.2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

0 = Program in Progress/Completed

The F-VPP status bit does not provide continuous indication of VPP

level. The WSM interrogates F-VPP level only after the Program or

Erase command sequences have been entered, and informs the

system if F-VPP has not been switched on. The F-VPP is also

checked before the operation is verified by the WSM. The F-VPP

status bit is not guaranteed to report accurate feedback between

VPPLK and VPP1 min.

When Program Suspend is issued, WSM halts execution and sets

both WSMS and PSS bits to 1. PSS bit remains set to 1 until a

Program Resume command is issued.

SR.1 = BLOCK LOCK STATUS

1 = Prog/Erase attempted on a locked block; Operation

aborted.

0 = No operation to locked blocks

If a program or erase operation is attempted to one of the locked

blocks, this bit is set by the WSM. The operation specified is

aborted and the device is returned to read status mode.

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

This bit is reserved for future use and should be masked out when

polling the status register.

Note: A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.

3.7

Block Locking

The instant, individual block locking feature that allows any flash block to be locked or unlocked

with no latency, which enables instant code and data protection.

This locking offers two levels of protection. The first level allows software-only control of block

locking (useful for data blocks that change frequently), while the second level requires hardware

interaction before locking can be changed (useful for code blocks that change infrequently).

The following sections will discuss the operation of the locking system. The term “state [XYZ]”

will be used to specify locking states; e.g., “state [001],” where X = value of WP#, Y = bit DQ1 of

the Block Lock status register, and Z = bit DQ0 of the Block Lock status register. Table 8 “Block

Locking State Transitions” on page 23 defines all of these possible locking states.

26 Aug 2005

20

Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family

Order Number: 252636, Revision: 004

Datasheet

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