PF28F1602C3TD70 Ver la hoja de datos (PDF) - Intel
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PF28F1602C3TD70 Datasheet PDF : 75 Pages
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C3 SCSP Flash Memory
Table 4.
Read Configuration Table
Item
Address
Data
Manufacturer Code (x16)
0x00000
0x0089
Device ID (See Appendix D)
0x00001
ID
Block Lock Configuration
0xXX002
LOCK
• Block Is Unlocked
• Block Is Locked
• Block Is Locked-Down
DQ0 = 0
DQ0 = 1
DQ1 = 1
Protection Register Lock
0x80
PR-LK
Protection Register (x16)
0x81-0x88
PR
Notes:
1.
See Section 3.7 for valid lock status outputs.
2.
“XX†specifies the block address of lock configuration being
read.
3.
See Section 3.8 for protection register information.
Notes
1, 2
3
Intel reserves other locations within the configuration address space for future use.
3.3
Read Status Register (70h)
The status register indicates the status of device operations, and the success/failure of that
operation.
1. After you issue the Read Status Register (70h) command, subsequent reads output data from
the status register until another command is issued.
2. To return to reading from the array, issue a Read Array (FFh) command.
The status register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 00h during a
Read Status Register command.
The contents of the status register are latched on the falling edge of F-OE# or F-CE#, whichever
occurs last. Latching on the falling edge prevents possible bus errors that might occur if status
register contents change while being read. F-CE# or F-OE# must be toggled with each subsequent
status read, or the status register does not indicate completion of a program or erase operation.
When the WSM is active, SR7 indicates the status of the WSM. The remaining bits in the status
register indicate whether the WSM was successful in performing the desired operation (see Table 6
“Flash Memory Status Register Definition†on page 19).
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
26 Aug 2005
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