PF28F1602C3TD70 Ver la hoja de datos (PDF) - Intel
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PF28F1602C3TD70 Datasheet PDF : 75 Pages
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C3 SCSP Flash Memory
operation. When the resume command is issued, the device will resume the program operation
first. Once the nested program operation is completed, an additional Resume command is required
to complete the block operation.
Table 5.
Flash Memory Command Definitions
Command
Read Array
Read Identifier
CFI Query
Read Status Register
Clear Status Register
Word Program
Block Erase/Confirm
Program/Erase Suspend
Program/Erase Resume
Lock Block
Unlock Block
Lock-Down Block
Protection Register Program
Lock Protection Register
Note
1
1, 2
1, 2
1
1
1, 3
1
1
1
1
1, 4
1
1
1
First Bus Cycle
Operation
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Address
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Data
FFh
90h
98h
70h
50h
40h/10h
20h
B0h
D0h
60h
60h
60h
C0h
C0h
Second Bus Cycle
Operation Address
Data
Read
IA
ID
Read
QA
QD
Read
X
SRD
Write
PA
PD
Write
BA
D0h
Write
Write
Write
Write
Write
BA
01h
BA
D0h
BA
2Fh
PA
PD
PA
FFFD
X = Don’t Care
PA = Program Address BA = Block Address IA = Identifier Address QA = Query Address
SRD = Status Register Data PD = Program Data
ID = Identifier Data
QD = Query Data
Notes:
1.
When writing commands, the upper data bus [DQ8–DQ15] should be either VIL or VIH, to minimize current draw.
2.
Following the Read Configuration or CFI Query commands, read operations output device configuration or CFI query
information, respectively.
3.
Either 40h or 10h command is valid, but the Intel standard is 40h.
4.
When unlocking a block, WP# must be held for three clock cycles (1 clock cycle after the second command bus cycle).
Table 6.
Flash Memory Status Register Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
26 Aug 2005
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