MT48LC4M32B2P-7 Ver la hoja de datos (PDF) - Micron Technology

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componentes Descripción

Fabricante

MT48LC4M32B2P-7

1 Meg x 32 x 4 Banks SDR SDRAM

Micron Technology 

128Mb: x32 SDRAM

Pin and Ball Assignments and Descriptions

Table 4: Pin/Ball Descriptions

Symbol

CLK

CKE

CS#

CAS#, RAS#,

WE#

DQM[3:0]

BA[1:0]

A[11:0]

DQ[31:0]

NC

VDDQ

VSSQ

VDD

VSS

Type Description

Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive

edge of CLK. CLK also increments the internal burst counter and controls the output registers.

Input

Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the

clock provides precharge power-down and SELF REFRESH operation (all banks idle), active

power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-

gress). CKE is synchronous except after the device enters power-down and self refresh modes,

where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-

cluding CLK, are disabled during power-down and self refresh modes, providing low standby

power. CKE may be tied HIGH.

Input

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-

coder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already

in progress will continue, and DQM operation will retain its DQ mask capability while CS# is

HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-

ered part of the command code.

Input Command inputs: CAS#, RAS#, and WE# (along with CS#) define the command being en-

tered.

Input

Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and

an output enable signal for read accesses. Input data is masked during a WRITE cycle. The

output buffers are High-Z (two-clock latency) during a READ cycle. DQM0 corresponds to

DQ[7:0], DQM1 corresponds to DQ[15:8], DQM2 corresponds to DQ[23:16], and DQM3 corre-

sponds to DQ[31:24]. DQM[3:0] are considered the same state when referenced as DQM.

Input Bank address inputs: BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRE-

CHARGE command is being applied.

Input

Address inputs: A[11:0] are sampled during the ACTIVE command (row address A[10:0]) and

READ or WRITE command (column address A[7:0] with A10 defining auto precharge) to select

one location out of the memory array in the respective bank. A10 is sampled during a PRE-

CHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selec-

ted by BA[1:0] (LOW). The address inputs also provide the op-code during a LOAD MODE

REGISTER command.

Input/ Data input/output: Data bus.

Output

– No connect: These pins should be left unconnected. Pin 70 is reserved for SSTL reference

voltage supply.

Supply DQ power supply: Isolated on the die for improved noise immunity.

Supply DQ ground: Provides isolated ground to DQs for improved noise immunity.

Supply Power supply: 3.3V ±0.3V.

Supply Ground.

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. U 04/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2001 Micron Technology, Inc. All rights reserved.

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