T35L6432A Ver la hoja de datos (PDF) - Taiwan Memory Technology
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T35L6432A Datasheet PDF : 15 Pages
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tm TE
CH
T35L6432A
READ TIMING
C LK
A DSP
A DSC
A DDRESS
GW , BW E,
BW 1- B W 4
CE
(NO TE2)
A DV
OE
Q
t KC
t KH t KL
t A D SS t A DS H
t A DS S t A D SH
t AS tAH
A1
A2
tW S tWH
t CES t CEH
A3
Bur st con tin ue d wi th
n ew b ase ad d re ss.
Des ele ct cy cle.
t AAS t AAH
AD V s usp e nd s bu rs t.
(NO TE 3)
t KQ LZ
tOE HZ
t O EQ
tOEL Z
t KQ
t KQ X
Hi g h-Z
t KQ
Q (A 1)
S in g le RE A D
Q (A 2)
(NOT E1)
Q(A 2+1)
t KQHZ
tK QX
Q (A 2+2)
Q(A2 +3 )
BUR S T RE A D
Q(A2)
Q (A 2+1)
Q(A 3)
Bu rst wr a ps a ro und
to i ts in ita l sta te.
DON'T CARE
UN D E FIN E D
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and
CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE
does not cause Q to be driven until after the following clock rising edge.
Taiwan Memory Technology, Inc. reserves the right P. 11
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision:A
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