T35L6432A Ver la hoja de datos (PDF) - Taiwan Memory Technology

Número de pieza

componentes Descripción

Fabricante

T35L6432A

64K x 32 SRAM

Taiwan Memory Technology 

tm TE

CH

T35L6432A

WRITE TIMING

CLK

A DSP

A DSC

A DDRESS

BW E,

BW 1- B W 4

t KC

t KH t KL

t A DS S t A DS H

t A D SS t A D S H

t AS tAH

A1

A2

BY T E W RIT E si g n als a r e

ig n or ed f or f ir st cy cle w hen

A DS P i n it i alte s bu r st.

GW

A DS C exte n ds b ur s t.

t A D SS t A D SH

tW S tWH

(N OT E 5)

A3

t WS t WH

CE

(NO TE 2)

A DV

OE

t CES t CEH

(NOT E 3)

t D S t DH

(NO TE 4)

AD V su sp nd s b u rst .

t AAS tAAH

D

Hi g h-Z

D(A1)

tO E HZ

Q

D(A2)

D(A2+1 )

(NOT E 1)

D(A2+ 1)

D(A2 +2)

D(A2+3 )

D(A3 )

D(A3+ 1)

D (A3+2 )

BUR ST RE A D

S in g le W RIT E

BU RS T W RIT E

E xte nd e d BU RST W RIT E

DON'T CARE

UN DE F IN E D

Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst

address following A2.

2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW , CE2 is LOW

and CE2 is HIGH. When CE is HIGH , CE2 is HIGH and CE2 is LOW.

3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time. This

prevents input/output data contention for the time period to the byte write enable inputs being

sampled.

4. ADV must be HIGH to permit a WRITE to the loaded address.

5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4 LOW.

Taiwan Memory Technology, Inc. reserves the right P. 12

to change products or specifications without notice.

Publication Date: DEC. 1998

Revision:A

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