T35L6432A Ver la hoja de datos (PDF) - Taiwan Memory Technology

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componentes Descripción

Fabricante

T35L6432A

64K x 32 SRAM

Taiwan Memory Technology 

tm TE

CH

READ/WRITE TIMING

CLK

A DSP

tKC

t KH t KL

t A DSS t A DSH

T35L6432A

A DSC

A DDRESS A 1

tAS tAH

A2

BW E

BW 1- B W 4

CE

(NO TE 2)

t C E S t C EH

A3

A4

tWS tWH

A5

A6

A DV

OE

D

Q

t KQ

t DS t DH

Hig h-Z

t KQLZ

Hi gh -Z

Q (A 1)

tOE HZ

D ( A 3)

Q(A 2)

t O ELZ

t KQ

Q(A3 )

D(A 5)

(NOT E1)

Q (A 4)

Q (A 4+1)

Q(A 4+2)

Q(A 4+3)

D(A6)

Back-t o-Back REA Ds

Si ng le W RIT E

Pas s -thr ough

REA D

BURST REA D

Ba c k - to- Ba c k

W RIT Es

DON'T CARE

UN DEFIN E D

Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst

address following A4.

2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW

and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC or ADV

cycle is performed.

4. GW is HIGH.

5. Back-to-back READs may be controlled by either ADSP or ADSC.

Taiwan Memory Technology, Inc. reserves the right P. 13

to change products or specifications without notice.

Publication Date: DEC. 1998

Revision:A

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