GT28F400B3B150 Ver la hoja de datos (PDF) - Intel
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GT28F400B3B150 Datasheet PDF : 49 Pages
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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
3.2.5
ERASE MODE
To erase a block, write the Erase Set-up and Erase
Confirm commands to the CUI, along with an
address identifying the block to be erased. This
address is latched internally when the Erase
Confirm command is issued. Block erasure results
in all bits within the block being set to “1.” Only one
block can be erased at a time.
The WSM will execute the following sequence of
internally timed events to:
1. Program all bits within the block to “0.”
2. Verify that all bits within the block are
sufficiently programmed to “0.”
3. Erase all bits within the block to “1.”
4. Verify that all bits within the block are
sufficiently erased.
While the erase sequence is executing, bit 7 of the
status register is a “0.”
When the status register indicates that erasure is
complete, check the Erase Status bit to verify that
the erase operation was successful. If the Erase
operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase
failure. If VPP was not within acceptable limits after
the Erase Confirm command was issued, the WSM
will not execute the erase sequence; instead, SR.5
of the status register is set to indicate an erase
error, and SR.3 is set to a “1” to identify that VPP
supply voltage was not within acceptable limits.
After an erase operation, clear the Status Register
(50H) before attempting the next operation. Any
CUI instruction can follow after erasure is
completed; however, to prevent inadvertent status
register reads, it is advisable to reset the flash to
read array after the erase is complete.
3.2.5.1
Suspending and Resuming Erase
Since an erase operation requires on the order of
seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in
order to read data from or program data to another
block in memory. Once the erase sequence is
started, writing the Erase Suspend command to the
CUI requests that the WSM pause the erase
sequence at a predetermined point in the erase
algorithm. The status register will indicate if/when
the erase operation has been suspended.
A Read Array/Program command can now be
written to the CUI in order to read/write data from/to
blocks other than that which is suspended. The
Program command can subsequently be
suspended to read yet another array location. The
only valid commands while erase is suspended are
Erase Resume, Program, Program Resume, Read
Array, or Read Status Register.
During erase suspend mode, the chip can be
placed in a pseudo-standby mode by taking CE# to
VIH. This reduces active current consumption.
Erase Resume continues the erase sequence when
CE# = VIL. As with the end of a standard erase
operation, the status register must be read and
cleared before the next instruction is issued.
3.2.5.2
VPP Supply Voltage during Erase
VPP supply voltage considerations are outlined in
Section 3.4.
PRELIMINARY
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