SPT561 Ver la hoja de datos (PDF) - Signal Processing Technologies
Número de pieza
componentes Descripción
Fabricante
SPT561 Datasheet PDF : 12 Pages
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feeds back to the bias current setup providing a current
shutdown feature when the output current approaches
250mA.
Figure 2: Simplified Circuit Diagram
+VCC
4
Ibias
Current Limit 10X Current Mirror
Q1
Vi
8
-VCC
+VCC
Q2
Q3
ierr
5pF
19
Cx
Rg
Rf
Q4
5pF
Io
23 Ro Vo
Io
Ibias
10X Current Mirror
Current Limit
21
-VCC
Developing the Performance Equations
The SPT561 is intended to provide both a controllable
voltage gain from input to output as well as a controllable
output impedance. It is best to treat these two operations
separately with no load in place. Then, with the no-load
gain and output impedance determined, the gain to the
load will simply be the no-load gain attenuated by the
voltage divider formed by the load and the equivalent
output impedance.
Figure 3 steps through the output impedance develop-
ment using an equivalent model of Figure 2. Offering an
equivalent, non-zero, output impedance into a matched
load allows the SPT561 to operate at lower internal
voltage swings for a given desired swing at the load. This
allows higher voltage swings to be delivered at the load
for a given power supply voltage at lower distortion levels
than an equivalent op amp needing to generate twice the
voltage swing actually desired at the matched load. This
improved distortion is specified and tested over a wide
range as shown in the specification listing.
Get both Vo and Io into terms of just the error current, ierr,
using:
V− = ierr Ri and
if
= ierr
+ V−
Rg
= ierr
1+
Ri
Rg
Vo
=
V− + if Rf
= ierr
Ri
+ Rf
1+
Ri
Rg
Vo
=
ierr
Rf
+ Ri
1+
Rf
Rg
and
Io
=
Gierr
+ if
=
ierr
G + 1+
Ri
Rg
then
Ro
≡
Vo
Io
=
Rf
+ Ri
1+
Rf
Rg
G + 1+ Ri
Rg
note that Ro
= Rf
G+1
Ri = 0
Figure 3: Output Impedance Derivation
Note that the Ro expression simplifies considerably if
Ri = 0. Also note that if the forward current gain were to go
to infinity, the output impedance would go to 0. This would
be the normal op amp topology with a very high internal
gain. The SPT561 achieves a non-zero Ro by
setting the internal forward gain to be a low, well
controlled, value.
Developing the No-Load Gain Expression
Taking the output impedance expression as one con-
straint setting the external resistor values, we now need
to develop the no-load voltage gain expression from the
non-inverting input to the output as the other constraint.
Figure 4 shows the derivation of the no load gain.
+
-
ierr V-
Rg
X1
Ri
Gierr
if
Rf
Ro Vo
lo
+
Vi
-
ierr V-
Rg
X1
Ri
Rf
Gierr
Vo
No load gain
Av
≡
Vo
Vi
SPT561
7
10/9/98
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