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UT1750AR12WCC

RISC Microprocessor

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Table 2. Interrupt Instruction Counter

Load Location

MASK- CAN USER

INTERRUPT LOCATION ABLE DISABLE

NUMBER

(HEX)

(Y/N)

(Y/N)

0

0400

N

N

1

0404

Y

N

2

0408

Y

Y

3

040C

Y

Y

4

0410

Y

Y

5

0414

N

N

6

0418

Y

Y

7

041C

Y

Y

8

0420

Y

Y

9

0424

Y

Y

10

0428

Y

Y

11

042C

Y

Y

12

0430

Y

Y

13

0434

Y

Y

14

0438

Y

Y

15

043C

Y

Y

When the UT1750AR is in the 1750 mode, the UT1750AR

handles the Interrupt Linkage Pointer Address and Interrupt

Service Pointer Address with the MIL-STD-1750A emulation

programming stored in the RISC PROMs. The addresses used

for each of the 16 interrupts are in table 3.

Any one of the 16 UT1750AR interrupts can be enabled at any

time during processor operation by setting the appropriate bit in

the Interrupt Mask Register (MK). If an interrupt occurs but

happens to have its corresponding bit masked out in the MK,

then the UT1750AR ignores that interrupt, although the Power-

Down Interrupt (Interrupt 0) and the Branch Executive Interrupt

(Interrupt 5) cannot be masked or disabled.

RISC Instruction Bus Cycle Operation

The Instruction Bus Cycle Operation refers to the only two RISC

instructions that can manipulate the data in the RISC memory.

These two RISC instructions are Store Register to Instruction

Memory (STRI) and Load Register from Instruction Memory

(LRI).

Table 3. UT1750AR MIL-STD-1750

Interrupt Pointer Addresses

INTERRUPT

NUMBER

0

INTERRUPT

LINKAGE

POINTER

ADDRESS

(HEX)

20

INTERRUPT

SERVICE

POINTER

ADDRESS

(HEX)

21

1

22

23

2

24

25

3

26

27

4

28

29

5

2A

2B

6

2C

2D

7

2E

2F

8

30

31

9

32

33

10

34

35

11

36

37

12

38

39

13

3A

3B

14

3C

3D

15

3E

3F

STRI Instruction Bus Cycle Operation

During an STRI instruction, RISC instruction data moves from

the UT1750AR to the RISC instruction memory. Figure 28 (see

page 28) shows the timing diagram of the signal relationships

for the UT1750AR during an STRI Instruction Bus Cycle

Operation.

Before the UT1750AR executes the STRI instruction, the

system programmer must load the UT1750AR’s Accumulator

(ACC) with the RISC address which will receive the data. When

the ACC is loaded with the address information, the UT1750AR

can begin executing the STRI instruction.

Executing the STRI instruction begins when the falling edge of

OSCIN signals the start of time period CK1. At the beginning

of CK1, the data previously stored in the ACC becomes a valid

address on the RISC address bus (RA0-RA20) and the STATE1

output becomes active, indicating the UT1750AR is executing

a RISC instruction.

27

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