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UT1750AR12WCC

RISC Microprocessor

Aeroflex UTMC 

Operand Bus Cycle Operation

The timing diagram in figure 26 (see page 24) shows signal

relationships for the UT1750AR during an operand bus cycle

operation. The UT1750AR performs one of four operations

involving bus cycles on the Operand busses. These bus cycles

are: (1) Memory Read; (2) Memory Write; (3) I/O Read; and

(4) I/O Write. The UT1750AR performs all four bus cycle

operations similarly. The M/IO and R/WR signals determine the

precise type of bus cycle operation. For the following

discussion, please refer to figure 26.

When the Operand bus arbitration process is complete and the

UT1750AR controls the Operand address and data busses, time

period CK3 begins. Because the UT1750AR took control of the

Operand busses at the beginning of time period CK3, BGACK

becomes active. STATE1 transitions from low to high and AS

goes active low. At the same time, the following signals become

valid: R/WR, M/IO, OP/IN, and the Operand Address Bus. The

three control signals determine the direction and type of bus

cycle taking place.

One-half clock cycle after the beginning of time period CK4 or

one full clock cycle after the start of time period CK3, DS goes

active low. After DS has gone low, the UT1750AR samples the

DTACK input on every subsequent rising edge of OSCIN to

determine the duration of CK4. This bus cycle terminates one-

half clock cycle after the rising edge of OSCIN when the

UT1750AR detects DTACK has gone active. The UT1750AR

also samples the MPROT and BTERR inputs on the same rising

edge of OSCIN. These two inputs indicate an error condition

and terminate the current bus cycle.

After the UT1750AR recognizes the current bus cycle is

finished, AS and DS become inactive (transition from low to

high) on the first rising edge of OSCIN after the end of time

period CK4. At this time, the Operand Address Bus (A0-A15)

and the Operand bus control signals (R/WR, M/IO, OP/IN)

select the memory or I/O location from which the Operand data

(D0-D15) is read, or to which the Operand data (D0-D15) is

written. The bus cycle completely ends one full clock cycle after

the end of time period CK4 (the next rising edge of STATE1)

when BGACK, R/WR, OP/IN, and the Operand address and

data busses enter a high-impedance state.

DMA Operation and Bus Arbitration

Figure 27 (see page 25) shows the timing diagram of the signal

relationships for the UT1750AR during a DMA operation. For

DMA operations, multiprocessor, and Operand bus arbitration

functions, the UT1750AR provides four active-low control

signals for managing the Operand bus and preventing bus

contention. These signals are Bus Request (BRG), Bus Grant

(BGNT), Bus Busy (BUSY), and Bus Grant Acknowledge

(BGACK).

Each of the four bus control signals provides a specific function

for controlling Operand bus operation. The function of each of

the four signals is given below.

Bus Request (BRO)

The UT1750AR generates BRG to indicate a request to use the

Operand busses. When the UT1750AR controls the Operand

busses, if it then requires successive bus cycles, multiple Bus

Requests are not generated. The UT1750AR retains control of

the busses by keeping the BGACK signal active until it no longer

requires the busses.

Bus Grant (BGNT)

An external arbiter generates this input indicating to the

UT1750AR that it has the highest priority. This informs the

UT1750AR to control the Operand busses as soon as the present

bus master relinquishes bus control by setting BUSY = 1.

Bus Busy (BUSY)

Another bus master generates BUSY input to the UT1750AR,

indicating another bus master is using the bus.

Bus Grant Acknowledge (BGACK)

The UT1750AR generates this signal to indicate it is the present

bus master. BGACK enters a high-impedance state when the

UT1750AR gives up control of the Operand busses.

The UT1750AR requests control of the Operand busses at the

beginning of time period CK2 by asserting BRG. On every

subsequent falling edge of OSCIN, the UT1750AR samples the

BGNT and BUSY inputs. When the UT1750AR detects on the

falling edge of OSCIN that BGNT has gone low and BUSY has

gone high, this tells the UT1750AR that it is the new bus master

and can now control the Operand busses. The UT1750AR locks

out any other bus master from controlling the Operand busses

by asserting BGACK at the beginning of time period CK3 and

holding BGACK active until it is ready to give up control of the

Operand busses. The UT1750AR holds the BGACK signal

active until the beginning of the CK3 time period of the next

bus cycle when the UT1750AR no longer controls the Operand

busses.

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