UT1750AR12WCC Ver la hoja de datos (PDF) - Aeroflex UTMC

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UT1750AR12WCC

RISC Microprocessor

Aeroflex UTMC 

3

Reserved.

2

BITF

Built-In-Test Fault. This bit

indicates the UT1750AR has

detectedahardwarebuilt-in-test

error. [0]

1-0

Spare BIT. The user defines

these bits as additional BIT

parameters. [0]

The Interrupt Mask Register (MK)

The Interrupt Mask Register (MK) (figure 16) contains one

mask bit for each of the 16 system interrupts. All bits in the MK

are set or reset under software control, although setting bits 15

and 10, Power Down Interrupt and Executive Call respectively,

has no effect on the UT1750AR’s operation because these

interrupts cannot be masked. The UT1750AR reads or loads the

MK with RISC I/O instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PM I FFEF T IT I I I I I I

W C N L I X L I N I N N ON ON

D H T P P C P MTM T T LT LT

N E OOOL U A 1B 2 3 1 4 2 5

MSB

LSB

Figure 16. The Interrupt Mask Register (MK)

The 1750 Status Word Register (SW)

The MIL-STD-1750A Instruction Set Architecture (ISA)

defines the Status Word Register (SW). The UT1750AR reads

and loads the SW with RISC I/O instructions. Figure 17 shows

the definitions of various bits in the SW.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit Definitions

BIT

NUMBER MNEMONIC

DESCRIPTION

15

C

Carry. This bit is set if the

result of an addition operation

generates a carry or if the result

of a subtraction generates no

borrow.

14

P

Positive. This bit is set if the

result of an operation is

greater than zero.

13

Z

Zero. This bit is set if the

result of an operation is equal

to zero.

12

N

Negative. This bit is set if the

result of an operation is less

than zero.

11 - 8

Reserved Bits.

7-4

PS3 -

Processor State. This PS0four

bit field determinesthe legal

illegal criteriafor privileged

instructions.

3-0

AS3 -

Address State. Used in AS0

conjunction with the optional

UT1750 MMUMemory

Management Unit,thisfour-bit

field determines the current

extended address page.

Note: If condition codes are turned on (default after reset) the

condition codes reflect the corresponding bits in the STATUS

register.

CONDITION RESERVED PROCESSOR ADDRESS

STATUS

STATE

STATE

(CS)

(PS)

(AS)

MSB

LSB

Figure 17. The 1750 Status Register (SW)

18

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