SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

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SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

Figure 1.0 illustrates the operation of the receive Speech Memory:

A slip condition is detected when the Write Pointer (W) and the Read pointer (R) of the

memory are nearly coincident, i.e. the Write pointer is within the Slip Limits (S+, S-). If

a slip condition is detected, a negative slip ( the next received frame is skipped) or a

positive slip (the previous received frame is read out twice) is performed at the System

Interface, depending on the difference between RCLK and SCLK, i.e. on the position of

pointer R and W within the memory.

To reduce delay, the Receive Speech Memory can be switched to one frame length. For

correct operation, System Clock SCLK and Synchronization Pulse SYPQ have to be

derived from the Receive Route Clock RCLK and the Receive Frame Synchronous Pulse

RFSPQ (PLL application). In Single Frame Mode, however, it is not possible to perform

a slip after the slip condition has been detected.

Receive Transparent Mode

If enabled, the frame aligner does not try to synchronise on the received data if

synchronisation is lost. The AIS to the System Interface is disabled. The data appears

on the System Interface synchronised to the System Clock (SCLK) as received.

Transmit path

The PCM data is received from the system internal highway at port DXI at 2048 kbps or

4096 kbps. The channel assignment is equivalent to the receive direction. Data in invalid

timeslots will be ignored.

Latching of data is controlled by the System Clock (SCLK) and the Synchronization Pulse

(SYPQ), in conjunction with the programmed offset values of the Transmit Timeslot/

Clockslot Counters.

The Transmit Route Clock (XRCLK) is derived directly from the system clock by an

internal clock divider. Consequently, the data received from the system interface is

switched through without the need of intermediate storage.

The parity generation/checking mechanism is symmetrical to the receive path. The

channel data is checked with the channel parity information generated internally or

externally (input at port XCHPAR with selectable parity type). Errors are reported to the

microprocessor interface. To avoid difficulties with external parity generation, the parity

signal for non-speech data (TS0 and TS16) is ignored.

Transmitter

The serial bit stream is then processed by the transmitter which has the following

functions:

- Frame/multiframe synthesis of one of the selectable framing formats

- Insertion of service and data link information.

- Remote Alarm generation

- CRC generation and insertion of CRC bits

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