DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

Número de pieza
componentes Descripción
Fabricante
SA9101
Sames
South African Micro Electronic Systems Sames
SA9101 Datasheet PDF : 40 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
SA9101
1. S bits: reserved for international use. If not used, these bits should be
i
fixed to ‘1’. Access to received information via bits SR4B7 and SR5B2.
Transmission is enabled via bits CR4B7 and CR5B2.
2. Fixed to ‘1’. Used for synchronization.
3. Remote Alarm Indication: In normal operation ‘0’; in alarm condition ’1'.
Transmission is done through CR4B5 and reception is indicated by interrupt
(maskable) and SR0B4.
4. S (Y) bits: Reserved for national use. If not used, they should be fixed at
n
‘1’. Access to received information via bits SR4B[4-0]. Transmission is
enabled via bits CR4B[4-0]
Synchronization procedure
Synchronization status is reported via µP-interface Status Register. Framing errors are
counted by the Framing Error Counter. Loss of synchronization is reached after detecting
3 consecutive incorrect FAS words or 3 consecutive incorrect service words (bit 2 1 in
timeslot 0 of every frame not containing the frame alignment word). When this occurs,
counting of framing errors will be stopped and AIS will be sent to the system internal
highway.
The re-synchronization procedure starts automatically after entering loss of synchronisation
state. Additionally, it may be invoked under user control via the µP-interface.
Synchronized state is reached after detecting:
- a correct FAS word in frame n,
- the presence of the correct service word (bit 2 = 1) in frame n+1
- a correct FAS word in frame n+2
Normal Synchronized operation starts with the data in frame n+2.
CRC-Multiframe
The multiframe structure shown in table 2 is enabled via µP-interface.
Multiframe
: 2 submultiframes = 2*8 frames
Multiframe alignment : bit 1 of frames 1,3,5,7,9,11 with the pattern ‘001011’
CRC bits
: bit 1 of frames 0,2,4,6,8,10,12,14
CRC block size
: 2048 bit (length of a submultiframe)
CRC procedure
: CRC4, according to CCITT Rec. G704
The CRC procedure is automatically invoked when the multiframe structure is enabled.
CRC errors in the received data stream are counted by the CRC Error Counter (max. one
error per sub-multiframe). This 8-bit counter is extendable to 10 bit length.
sames
15/40

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]