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1EDI2004AS Ver la hoja de datos (PDF) - Infineon Technologies

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1EDI2004AS Datasheet PDF : 138 Pages
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EiceDRIVERTM SIL
1EDI2004AS
Functional Description
GATE
Input pin used to monitor the IGBT gate voltage.
OSD
Output Stage Disable input. A High Level on this pin tristates the output stage. An internal weak pull-down
resistor to VGND2 drives this input to Low state in case the pin is floating.
DACLP
Output pin used to disable the active clamping function of the booster.
DEBUG
Debug input pin. This pin is latched at power-up. When a High level is detected on this pin, the device enters a
special mode where it can be operated without SPI interface. This feature is for development purpose only.
This pin should normally be tied to VGND2. An internal weak pull-down resistor to VGND2 drives this input to Low
state in case the pin is floating.
IREF2
Reference input of the secondary chip. This pin shall be connected to VGND2 via an external resistor.
VREG
Reference Output voltage. This pin shall be connected to an external capacitance to VGND2.
NUV2
VCC2 not valid notification signal (Open Drain). This signal drives a low level when VCC2 is below VUVLO2L or when
the internal 5V digital supply is not valid. When both supplies are valid, this pin is in high impedance state. This
pin shall be connected externally to a 5V reference with a pull-up resistance to ensure level read-out over the
respective register. The pin can be connected also to respective ground potential (This enables usage together
with OSD pin).
AMCLP
Active Miller Clamping External Enable Output. The signal goes to High level when VGATE is lower than VGATE1
during turn-off.
2.2.2.3 Pull Devices
Some of the pins are connected internally to pull-up or pull-down devices. This is summarized in Table 2.
Table 2
Signal
INP
INSTP
EN
SCLK
SDI
NCS
Internal pull devices
Data Sheet
Device
Weak pull down to VREF0
Weak pull down to VREF0
Weak pull down to VREF0
Weak pull up to VCC1
Weak pull up to VCC1
Weak pull up to VCC1
15
Rev. 2.0
2019-01-16

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