TSL2581CS Ver la hoja de datos (PDF) - austriamicrosystems AG
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TSL2581CS Datasheet PDF : 33 Pages
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TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134A − JULY 2012
ID Register (12h)
The ID register provides the value for both the part number and silicon revision number for that part number.
It is a read-only register whose value never changes.
Table 11. ID Register
Bit : 7
6
5
4
3
2
1
0
Address
12h
lid FIELD
PARTNO
REVNO
PARTNO
REVNO
BITS
7:4
3:0
DESCRIPTION
Part Number Identification: field value 1001b
Revision number identification
Reset
−−
a ADC Channel Data Registers (14h − 17h)
v The ADC channel data are expressed as 16-bit values spread across two registers. The ADC channel 0 data
ill registers, DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value of
channel 0. Registers DATA1LOW and DATA1HIGH provide the lower and upper bytes, respectively, of the ADC
value of channel 1. All channel data registers are read-only and default to 00h on power up.
G st REGISTER
A t DATA0LOW
DATA0HIGH
s n DATA1LOW
e DATA1HIGH
Table 12. ADC Channel Data Registers
ADDRESS
14h
15h
16h
17h
BITS
7:0
7:0
7:0
7:0
DESCRIPTION
ADC channel 0 lower byte
ADC channel 0 upper byte
ADC channel 1 lower byte
ADC channel 1 upper byte
m t The upper byte data registers can only be read following a read to the corresponding lower byte register. When
a n the lower byte register is read, the upper eight bits are strobed into a shadow register, which is read by a
subsequent read to the upper byte. The upper register will read the correct value even if additional ADC
o integration cycles end between the reading of the lower and upper registers.
c NOTE: The Read Word protocol can be used to read byte-paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well as
the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16-bit ADC value in a single transaction
l Manual Integration Timer Registers (18h − 19h)
a The MANUAL INTEGRATION TIMER registers provide the number of cycles in 10.9 μs increments that
ic occurred during a manual start/stop integration period. The timer is expressed as a 16-bit value across two
registers. See CONTROL and TIMING Registers for further instructions in configuring a manual integration.
The maximum time that can be derived without an overflow is 714.3 ms.
nTable 13. Manual Integration Timer Registers
h Bit: 7
6
5
4
3
2
1
c Address
18h 19h
TIMER
Te REGISTER ADDRESS BITS
DESCRIPTION
0
Reset
00h
TIMERLOW
18h
7:0
Manual Integration Timer lower byte
TIMERHIGH
19h
7:0
Manual Integration Timer upper byte
The LUMENOLOGY r Company
r
Copyright E 2012, TAOS Inc.
r
www.taosinc.com
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