TSL2581CS Ver la hoja de datos (PDF) - austriamicrosystems AG
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TSL2581CS Datasheet PDF : 33 Pages
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TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134A − JULY 2012
Interrupt Threshold Registers (03h − 06h)
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison
function for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low
threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses
above the high threshold specified, an interrupt is asserted on the interrupt pin. Registers TLLOW and
TLHIGH provide the low byte and high byte, respectively, of the lower interrupt threshold. Registers THLOW
and THHIGH provide the low and high bytes, respectively, of the upper interrupt threshold. The high and low
bytes from each set of registers are combined to form a 16-bit threshold value. The interrupt threshold registers
default to 00h on power up.
lid REGISTER
a TLLOW
v TLHIGH
THLOW
ill THHIGH
Table 9. Interrupt Threshold Registers
ADDRESS
3h
4h
5h
6h
BITS
7:0
7:0
7:0
7:0
DESCRIPTION
ADC channel 0 lower byte of the low threshold
ADC channel 0 upper byte of the low threshold
ADC channel 0 lower byte of the high threshold
ADC channel 0 upper byte of the high threshold
NOTE: Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the Send Byte protocol should
t not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the
COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desired.
G s The Write Word protocol should be used to write byte-paired registers. For example, the TLLOW and TLHIGH registers (as well as the
THLOW and THHIGH registers) can be written together to set the 16-bit ADC value in a single transaction.
s A nt Analog Register (07h)
e The ANALOG register provides eight bits of control to the analog block. These bits control the analog gain
m t settings of the device.
a n Bit: 7
o Address
c 07h
FIELD
l Resv
BITS
7:3
Technica Gain
2:0
Table 10. Analog Register
6
5
4
3
2
1
0
RESV
GAIN
DESCRIPTION
Reserved. Write as 0.
Gain Control. Sets the analog gain of the device according to the following table.
FIELD VALUE
x00
x01
x10
GAIN VALUE
1×
8×
16×
x11
111×
Reset
00h
Copyright E 2012, TAOS Inc.
14
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The LUMENOLOGY r Company
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