DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

TSL2581CS Ver la hoja de datos (PDF) - austriamicrosystems AG

Número de pieza
componentes Descripción
Fabricante
TSL2581CS
AmsAG
austriamicrosystems AG AmsAG
TSL2581CS Datasheet PDF : 33 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134A − JULY 2012
Interrupt Register (02h)
The INTERRUPT register controls the extensive interrupt capabilities of the device. The open-drain interrupt
pin is active low and requires a pull-up resistor to VBUS in order to pull high in the inactive state. The Interrupt
Register provides control over when a meaningful interrupt will occur. The concept of meaningful change can
be defined by the user both in terms of light intensity and time, or persistence of that change in intensity. The
value must cross the threshold (as configured in the Threshold Registers 03h through 06h) and persist for some
period of time, as outlined in Table 8.
When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value
outside of the programmed threshold window. The interrupt is active-low and remains asserted until cleared by
lid writing an 11 in the TRANSACTION field in the COMMAND register.
Note: Interrupts are based on the value of Channel 0 only.
va Bit: 7
ill Address
02h
Resv
6
INTR_STOP
Table 6. Interrupt Control Register
5
4
3
2
1
Resv
INTR
PERSIST
0
Reset
00h
t FIELD
Resv
G s INTR_STOP
s A nt Resv
INTR
e PERSIST
BITS
7
6
5
4
3:0
DESCRIPTION
Reserved. Write as 0.
Stop ADC integration on interrupt. When high, ADC integration will stop once an interrupt is asserted. To
resume operation (1) de-assert ADC_EN using CONTROL register, (2) clear interrupt using COMMAND
register, and (3) re-assert ADC_EN using CONTROL register. Note: Use this bit to isolate a particular
condition when the sensor is continuously integrating.
Reserved. Write as 0.
INTR Control Select. This field determines mode of interrupt logic according to Table 7, below.
Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 8, below.
am nt Table 7. Interrupt Control Select
INTR FIELD VALUE
o 0
Technical c 1
READ VALUE
Interrupt output disabled
Level Interrupt
Copyright E 2012, TAOS Inc.
12
r
www.taosinc.com
The LUMENOLOGY r Company
r

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]