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FL7930CMX-G

Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting

ON Semiconductor 

Applications Information

1. Startup: Normally, supply voltage (VCC) of a PFC

block is fed from the additional power supply, which can

be called standby power. Without this standby power,

auxiliary winding for zero current detection can be used

as a supply source. Once the supply voltage of the PFC

block exceeds 12 V, internal operation is enabled until

the voltage drops to 8.5 V. If VCC exceeds VZ, 20 mA

current is sinking from VCC.

VINPFC

PFC Inductor

VOUTPFC

Aux. Winding

External VCC circuit

when no standby power exists

FL7930 Rev.00

VREF

VBIAS

2.5VREF VCC’

Internal

Bias

H:open

reset

-

+

8.5 12

VCC

8

VZ

VTH(S/S) 20mA

Figure 22. Startup Circuit

2. INV Block: Scaled-down voltage from the output is

the input for the INV pin. Many functions are embedded

based on the INV pin: transconductance amplifier,

output OVP comparator, disable comparator, and output

UVLO comparator.

For the output voltage control, a transconductance

amplifier is used instead of the conventional voltage

amplifier. The transconductance amplifier (voltage-

controlled current source) aids the implementation of

the OVP and disable functions. The output current of

the amplifier changes according to the voltage

difference of the inverting and non-inverting input of

the amplifier. To cancel down the line input voltage

effect on power factor correction, the effective control

response of the PFC block should be slower than the

line frequency and this conflicts with the transient

response of controller. Two-pole one-zero type

compensation can meet both requirements.

The OVP comparator shuts down the output drive block

when the voltage of the INV pin is higher than 2.675 V

and there is 0.175 V hysteresis. The disable comparator

disables operation when the voltage of the inverting input

is lower than 0.35 V and there is 100 mV hysteresis. An

external small-signal MOSFET can be used to disable the

IC, as shown in Figure 23. The IC operating current

decreases to reduce power consumption if the IC is

disabled. Figure 24 is the timing chart of the internal

circuit near the INV pin when rated PFC output voltage

is 390 VDC and VCC supply voltage is 15 V.

UVLO

disable

OVP

2.5 2.675

disable

INV open 0.35 0.45

high

VCC’

2.051 2.240

2

RDY

3

COMP

2.240V/2.051V

2.675V/2.5V

0.45V/0.35V

2.5V

INV

1

FL7930 Rev.00

VOUTPFC

disable

Figure 23.

VOUTPFC

390Vdc

349V

Circuit Around INV Pin

413V

390V

320V

70V

VINV

2.50V

2.24V

0.45V

VCC

15V

2.0V

IOUTCOMP

Disable

Current sourcing

2.65V

55V

2.50V

2.051V

0.35V

I sinking

Current sourcing

VRDY

Voltage is decided by pull-up voltage.

OVP

Vcc<2V, internal logic is not alive.

- RDY pin is floating, so pull up voltage is shown.

- Internal signals are unknown.

t

Figure 24. Timing Chart for INV Block

3. RDY Output: When the INV voltage is higher than

2.24 V, RDY output is triggered HIGH and lasts until the

INV voltage is lower than 2.051 V. When input AC

voltage is quite high, for example 240 VAC, PFC output

voltage is always higher than RDY threshold, regardless

of boost converter operation. In this case, the INV

voltage is already higher than 2.24 V before PFC VCC

touches VSTART; however, RDY output is not triggered to

HIGH until VCC touches VSTART. After boost converter

operation stops, RDY is not pulled LOW because the

INV voltage is higher than the RDY threshold. When VCC

of the PFC drops below 5 V, RDY is pulled LOW even

though PFC output voltage is higher than threshold. The

RDY pin output is open drain, so needs an external pull-

up resistor to supply the proper power source. The RDY

pin output remains floating until VCC is higher than 2 V.

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