CY14B108N-ZSP25XCT Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

CY14B108N-ZSP25XCT

8 Mbit (1024K x 8/512K x 16) nvSRAM

Cypress Semiconductor 

CY14B108L, CY14B108N

Figure 6. SRAM Read Cycle #2: CE and OE Controlled[3, 10, 14]

Address

CE

OE

BHE, BLE

Data Output

High Impedance

ICC

Standby

Address Valid

tRC

tACE

tAA

tLZCE

tLZOE

tDOE

tDBE

tLZBE

tPU

Active

tHZCE

tHZOE

tHZBE

Output Data Valid

tPD

$GGUHVV

&(

%+(%/(

:(

'DWD,QSXW

'DWD2XWSXW

Figure 7. SRAM Write Cycle #1: WE Controlled[3, 13, 14, 15]

W:&

$GGUHVV9DOLG

W6&(

W+$

W6$

3UHYLRXV'DWD

W%:

W$:

W3:(

W+=:(

W6'

W+'

,QSXW'DWD9DOLG

W/=:(

+LJK,PSHGDQFH

Note

15. CE or WE must be >VIH during address transitions.

Document #: 001-45523 Rev. *D

Page 11 of 24

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