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AD9639BCPZ-170 Datasheet PDF : 36 Pages
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Data Sheet
AD9639
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless
otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Voltage Range
Temp
Full
Full
Full
Internal Common-Mode Bias
Full
Input Common-Mode Voltage
Full
High Level Input Voltage (VIH)
Full
Low Level Input Voltage (VIL)
Full
High Level Input Current (IIH)
Full
Low Level Input Current (IIL)
Full
Differential Input Resistance
25°C
Input Capacitance
25°C
LOGIC INPUTS (PDWN, CSB, SDI/SDIO,
SCLK, RESET, PGMx)2
Logic 1 Voltage
Full
Logic 0 Voltage
Full
Logic 1 Input Current (CSB)
Full
Logic 0 Input Current (CSB)
Full
Logic 1 Input Current
Full
(PDWN, SDI/SDIO, SCLK,
RESET, PGMx)
Logic 0 Input Current
Full
(PDWN, SDI/SDIO, SCLK,
RESET, PGMx)
Input Resistance
25°C
Input Capacitance
25°C
LOGIC OUTPUT (SDO)
Logic 1 Voltage
Full
Logic 0 Voltage
Full
DIGITAL OUTPUTS (DOUT + x, DOUT − x)
Logic Compliance
Differential Output Voltage
Full
Common-Mode Voltage
Full
AD9639BCPZ-170
Min
Typ
Max
LVPECL/LVDS/CMOS
0.2
6
AVDD −
0.3
AVDD +
1.6
1.2
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
16
20
24
4
0.8 ×
AVDD
0
−60
55
0.2 ×
AVDD
0
30
4
1.2
AVDD +
0.3
0
0.3
CML
0.8
DRVDD/2
AD9639BCPZ-210
Min
Typ
Max
LVPECL/LVDS/CMOS
0.2
6
AVDD −
0.3
AVDD +
1.6
1.2
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
16
20
24
4
0.8 ×
AVDD
0
−60
55
0.2 ×
AVDD
0
30
4
1.2
AVDD +
0.3
0
0.3
CML
0.8
DRVDD/2
Unit
V p-p
V
V
V
V
µA
µA
kΩ
pF
V
V
µA
µA
µA
µA
kΩ
pF
V
V
V
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
2 Specified for 13 SDI/SDIO pins on the same SPI bus.
Rev. C | Page 5 of 36
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