AD9639BCPZ-170 Ver la hoja de datos (PDF) - Analog Devices
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AD9639BCPZ-170 Datasheet PDF : 36 Pages
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AD9639
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless
otherwise noted.
Table 4.
Parameter1
CLOCK
Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
DATA OUTPUT PARAMETERS
Data Output Period or UI
(DOUT + x, DOUT − x)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (tLOCK)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)2
Pipeline Latency
Data Rate per Channel (NRZ)
Deterministic Jitter
Random Jitter
Channel-to-Channel Bit Skew
Channel-to-Channel Packet Skew3
Output Rise/Fall Time
TERMINATION CHARACTERISTICS
Differential Termination Resistance
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
OUT-OF-RANGE RECOVERY TIME
Temp
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
AD9639BCPZ-170
Min
Typ
Max
100
170
2.65
2.9
2.65
2.9
1/(20 × fCLK)
50
0.8
4
250
50
40
3.4
10
6
0
±1
50
100
1.2
0.2
1
AD9639BCPZ-210
Min
Typ
Max
100
210
2.15
2.4
2.15
2.4
1/(20 × fCLK)
50
0.8
4
250
50
40
4.2
10
6
0
±1
50
100
1.2
0.2
1
Unit
MSPS
ns
ns
Seconds
%
UI
µs
ns
μs
CLK cycles
Gbps
ps
ps rms
Seconds
CLK cycles
ps
Ω
ns
ps rms
CLK cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
2 Receiver dependent.
3 See the Serial Data Frame section.
Rev. C | Page 6 of 36
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