APA3160A Ver la hoja de datos (PDF) - Anpec Electronics
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APA3160A Datasheet PDF : 38 Pages
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APA3160A
Function Description (Cont.)
Start/Stop Period Register (0x1A) (Cont.)
Table 13. Start/Stop Period Register (0x1A)
D7 D6 D5 D4 D3 D2 D1
-
-
-
1
0
0
0
-
-
-
1
0
0
0
-
-
-
1
0
0
1
-
-
-
1
0
0
1
-
-
-
1
0
1
0
-
-
-
1
0
1
0
-
-
-
1
0
1
1
-
-
-
1
0
1
1
-
-
-
1
1
0
0
-
-
-
1
1
0
0
-
-
-
1
1
0
1
-
-
-
1
1
0
1
-
-
-
1
1
1
0
-
-
-
1
1
1
0
-
-
-
1
1
1
1
-
-
-
1
1
1
1
D0
FUNCTION
0 164.6ms 50% duty cycle start/stop period
1 239.4ms 50% duty cycle start/stop period
0 314.2ms 50% duty cycle start/stop period
1 403.9ms 50% duty cycle start/stop period
0 538.6ms 50% duty cycle start/stop period
1 703.4ms 50% duty cycle start/stop period
0 942.5ms 50% duty cycle start/stop period
1 1256.6ms 50% duty cycle start/stop period
0 1728.1ms 50% duty cycle start/stop period
1 2513.6ms 50% duty cycle start/stop period
0 3299.1ms 50% duty cycle start/stop period
1 4241.7ms 50% duty cycle start/stop period
0 5655.6ms 50% duty cycle start/stop period
1 7383.7ms 50% duty cycle start/stop period
0 9897.3ms 50% duty cycle start/stop period
0 13196.4ms 50% duty cycle start/stop period
Input Multiplexer Register (0x20)
This register controls the modulation scheme (BD mode) as well as the routing of I2S audio to the internal channels.
Table 14. Input Multiplexer Register (0x20)
D7 D6 D5 D4 D3 D2 D1 D0
FUNCTION
0
-
-
-
-
-
-
- Reserved
1
-
-
-
-
-
-
- Channel 1 BD mode
-
0
0
0
-
-
-
- SDIN-L to Channel 1
-
0
0
1
-
-
-
- SDIN-R to Channel 1
-
0
1
0
-
-
-
- Reserved
-
0
1
1
-
-
-
- Reserved
-
1
0
0
-
-
-
- Reserved
-
1
0
1
-
-
-
- Reserved
-
1
1
0
-
-
-
- Ground (0) to channel 1
-
1
1
1
-
-
-
- Reserved
-
-
-
-
0
-
-
- Reserved
-
-
-
-
1
-
-
- Channel-2 BD mode
-
-
-
-
-
0
0
0 SDIN-L to Channel 2
-
-
-
-
-
0
0
1 SDIN-R to Channel 2
Copyright © ANPEC Electronics Corp.
27
Rev. A.6 - Jan., 2013
www.anpec.com.tw
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