APA3160A Ver la hoja de datos (PDF) - Anpec Electronics

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Fabricante

APA3160A

20W Stereo Digital Class-D Audio Power Amplifier

Anpec Electronics 

APA3160A

Function Description (Cont.)

Clock Control Register (0x00)

The clocks and data rates are automatically determined by the APA3160A. The clock control register contains the auto-

detected clock status. Bits D7-D5 reflect the sample rate. Bits D4-D2 reflect the MCLK frequency.

Table 2. Clock Control Register (0x00)

D7 D6 D5 D4 D3 D2 D1 D0

FUNCTION

0

0

0

-

-

-

-

- fS=32kHz sample rate

0

0

1

-

-

-

-

- fS=88.2/96kHz sample rate

0

1

0

-

-

-

-

- fS=176.4/192kHz sample rate

0

1

1

-

-

-

-

- fS=44.1/48kHz sample rate

1

0

0

-

-

-

-

-

Reserved (Note 5)

1

0

1

-

-

-

-

-

Reserved (Note 5)

1

1

0

-

-

-

-

-

Reserved (Note 5)

1

1

1

-

-

-

-

-

Reserved (Note 5)

-

-

-

0

0

0

-

- MCLK frequency=64xfS

-

-

-

0

0

1

-

- MCLK frequency=128xfS

-

-

-

0

1

0

-

- MCLK frequency=192xfS (Note 6)

-

-

-

0

1

1

-

- MCLK frequency=256xfS (Note 6)

-

-

-

1

0

0

-

- MCLK frequency=384xfS(Note 7)

-

-

-

1

0

1

-

- MCLK frequency=512xfS(Note 7)

-

-

-

1

1

0

-

-

Reserved (Note 5)

-

-

-

1

1

1

-

-

Reserved (Note 5)

-

-

-

-

-

-

0

-

Reserved (Note 5)

-

-

-

-

-

-

-

0 Reserved (Note 5)

Note (5): Reserved registers should not be accessed.

Note (6): Rate only available for 32k/44.1k/48k/88.2k/96kHz sample rates.

Note (7): Rate only available for 32k/44.1k/48k sample rates.

Copyright © ANPEC Electronics Corp.

22

Rev. A.6 - Jan., 2013

www.anpec.com.tw

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