MC100LVEL31(2016) Ver la hoja de datos (PDF) - ON Semiconductor
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MC100LVEL31 Datasheet PDF : 6 Pages
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MC100LVEL31
S1
D2
CLK 3
R4
S
D
Flip Flop
R
8 VCC
7Q
6Q
5 VEE
Figure 1. Logic Diagram and Pinout Assignment
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK
Q, Q
D
R
S
VCC
VEE
ECL Clock Input
ECL Differential Data Outputs
ECL Data Input
ECL Reset Input
ECL Set Input
Positive Supply
Negative Supply
Table 2. TRUTH TABLE
D S R CLK Q
Q
LLL
HL L
XHL
XLH
XHH
Z
L
H
Z
H
L
X
H
L
X
L
H
X Undef Undef
Z = LOW to HIGH Transition
X = Don’t Care
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply
VEE
NECL Mode Power Supply
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
Iout
Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI ≤ VCC
VI ≥ VEE
8 to 0
V
−8 to 0
V
6 to 0
V
−6 to 0
50
mA
100
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
SOIC−8 NB
−40 to +85
−65 to +150
190
130
°C
°C
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
TSSOP−8
TSSOP−8
41 to 44 ±5%
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
TSSOP−8
41 to 44 ±5%
°C/W
Tsol
Wave Solder (Pb-Free)
< 2 to 3 sec @ 260°C
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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