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NX25P10

1M-BIT, 2M-BIT AND 4M-BIT Serial Flash Memory with 40MHz SPI

NexFlash -> Winbond Electronics 

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10, NX25P20 AND NX25P40

Write Status Register (01h)

The Write Status Register instruction allows the Status

Register to be written. A Write Enable instruction must

previously have been executed for the device to accept the

Write Status Register Instruction (Status Register bit WEL

must equal 1). Once write enabled, the instruction is entered

by driving CS low, sending the instruction code “01h”, and

then writing the status register data byte as illustrated in

figure 7. The Status Register bits are shown in figure 3 and

described earlier in this data sheet.

For the NX25P40, only non-volatile Status Register bits

STP, BP2, BP1 and BP0 (bits 7, 4, 3 and 2) can be written

to. For the NX25P20 and NX25P10 only Status Register bits

STP, BP1 and BP0 (bits 7, 3 and 2) can be written to. All

other Status Register bit locations are read-only and will not

be affected by the Write Status Register instruction.

The CS pin must be driven high after the eighth bit of the last

byte has been latched. If this is not done the Write Status

Register instruction will not be executed. After CS is driven

high, the self-timed Write Status Register cycle will com-

mence for a time duration of tW (See AC Characteristics).

While the Write Status Register cycle is in progress, the

1 Read Status Register instruction may still accessed to

check the status of the BUSY bit. The BUSY bit is a 1 during

the Write Status Register cycle and a 0 when the cycle is

finished and ready to accept other instructions again. After

2 the Write Register cycle has started the Write Enable Latch

(WEL) bit in the Status Register will be cleared to 0.

The Write Status Register instruction allows the Block

Protect bits (BP2, BP1 and BP0) to be set for protecting all,

3 a portion, or none of the memory from erase and program

instructions. Protected areas become read-only (see table

2). The Write Status Register instruction also allows the

Status Register Protect bit (SRP) to be set. This bit is used

4 in conjunction with the Write Protect (WP) pin to disable

writes to the status register. When the SRP bit is set to a 0

state (factory default) the WP pin has no control over the

status register. When the SRP pin is set to a 1, the Write

5 Status Register instruction is locked out while the WP pin

is low. When the WP pin is high the Write Status Register

instruction is allowed.

6

CS

Mode 3

CLK Mode 0

DI

DO

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction (01h)

Status Register In

76543210

*

High Impedance

* = MSB

Figure 7. Write Status Register Instruction Sequence Diagram

7

8

9

10

11

12

NexFlash Technologies, Inc.

13

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

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