M95010 Ver la hoja de datos (PDF) - STMicroelectronics

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M95010

4/2/1 Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95040, M95020, M95010

Data Protection and Protocol Control

To help protect the device from data corruption in

noisy or poorly controlled environments, a number

of safety features have been built in to the device.

The main security measures can be summarized

as follows:

– The WEL bit is reset at power-up.

– Chip Select (S) must rise after the eighth clock

count (or multiple thereof) in order to start a non-

volatile Write cycle (in the memory array or in

the Status Register).

– Accesses to the memory array are ignored dur-

ing the non-volatile programming cycle, and the

programming cycle continues unaffected.

– Invalid Chip Select (S) and Hold (HOLD) transi-

tions are ignored.

For any instruction to be accepted and executed,

Chip Select (S) must be driven High after the rising

edge of Serial Clock (C) that latches the last bit of

the instruction, and before the next rising edge of

Serial Clock (C).

For this, “the last bit of the instruction” can be the

eighth bit of the instruction code, or the eighth bit

of a data byte, depending on the instruction (ex-

cept in the case of RDSR and READ instructions).

Moreover, the "next rising edge of CLOCK" might

(or might not) be the next bus transaction for some

other device on the bus.

When a Write cycle is in progress, the device pro-

tects it against external interruption by ignoring

any subsequent READ, WRITE or WRSR instruc-

tion until the present cycle is complete.

Table 3. Write-Protected Block Size

Status Register Bits

BP1

BP0

Protected Block

0

0

none

0

1

Upper quarter

1

0

Upper half

1

1

Whole memory

Array Addresses Protected

M95040

M95020

M95010

none

none

none

180h - 1FFh

C0h - FFh

060h - 7Fh

100h - 1FFh

80h - FFh

040h - 7Fh

000h - 1FFh

00h - FFh

000h - 7Fh

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