PSD853F5VA-70JIT Ver la hoja de datos (PDF) - STMicroelectronics

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Fabricante

PSD853F5VA-70JIT

Flash in-system programmable (ISP) ipherals for 8-bit MCUs, 5 V

STMicroelectronics 

Pin description

PSD8XXFX

Table 3. PLCC52 pin description (1) (continued)

Pin name Pin Type

Description

These pins make up port A. These port pins are configurable and can have the

following functions:

PA0

29

MCU I/O – write to or read from a standard output or input port.

PA1

28

CPLD macrocell (McellAB0-7) outputs.

PA2

27

Inputs to the PLDs.

PA3

25

Latched address outputs (see Table 7).

PA4

24

I/O Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA

in burst mode.

PA5

23

As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.

PA6

22

t(s) PA7

21

D0/A16-D3/A19 in M37702M2 mode.

Peripheral I/O mode.

Note: PA0-PA3 can only output CMOS signals with an option for high slew rate.

However, PA4-PA7 can be configured as CMOS or Open Drain outputs.

uc PB0

7

rod PB1

6

These pins make up port B. These port pins are configurable and can have the

following functions:

PB2

5

MCU I/O – write to or read from a standard output or input port.

P PB3

4

CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.

te I/O

PB4

3

Inputs to the PLDs.

le PB5

2

Latched address outputs (see Table 7).

o PB6

52

bs PB7

51

Note: PB0-PB3 can only output CMOS signals with an option for high slew rate.

However, PB4-PB7 can be configured as CMOS or Open Drain outputs.

O PC0 pin of port C. This port pin can be configured to have the following functions:

- MCU I/O – write to or read from a standard output or input port.

t(s) CPLD macrocell (McellBC0) output.

PC0

20 I/O

Input to the PLDs.

c TMS input(2) for the JTAG Serial Interface.

du This pin can be configured as a CMOS or Open Drain output.

roPC1 pin of port C. This port pin can be configured to have the following functions:

P MCU I/O – write to or read from a standard output or input port.

te CPLD macrocell (McellBC1) output.

PC1

19 I/O

le Input to the PLDs.

o TCK input(2) for the JTAG Serial Interface.

s This pin can be configured as a CMOS or Open Drain output.

Ob PC2 pin of port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

PC2

18 I/O CPLD macrocell (McellBC2) output.

Input to the PLDs.

This pin can be configured as a CMOS or Open Drain output.

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Doc ID 7833 Rev 7

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