PSD853F5VA-70JIT Ver la hoja de datos (PDF) - STMicroelectronics

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PSD853F5VA-70JIT

Flash in-system programmable (ISP) ipherals for 8-bit MCUs, 5 V

STMicroelectronics 

PSD8XXFX

PSD architectural overview

3.4

I/O ports

The PSD has 27 individually configurable I/O pins distributed over the four ports (Port A, B,

C, and D). Each I/O pin can be individually configured for different functions. ports can be

configured as standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using

multiplexed address/data buses.

The JTAG pins can be enabled on port C for in-system programming (ISP).

Ports A and B can also be configured as a data port for a non-multiplexed bus.

3.5

MCU bus interface

PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed

) address/data buses. The device is configured to respond to the MCU control signals, which

t(s are also used as inputs to the PLDs. For examples, please see Section 15.4: MCU bus

c interface examples.

du Table 4. PLD I/O

ro Name

te P Decode PLD (DPLD)

le Complex PLD (CPLD)

Inputs

73

73

Outputs

17

19

Product terms

42

140

Obso 3.6

JTAG port

) - In-system programming (ISP) can be performed through the JTAG signals on port C. This

t(s serial interface allows complete programming of the entire PSD device. A blank device can

be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can

uc be multiplexed with other functions on port C. Table 5 indicates the JTAG pin assignments.

Prod 3.7

In-system programming (ISP)

teUsing the JTAG signals on port C, the entire PSD device can be programmed or erased

lewithout the use of the MCU. The primary Flash memory can also be programmed in-system

o by the MCU executing the programming algorithms out of the secondary memory, or SRAM.

s The secondary memory can be programmed the same way by executing out of the primary

Ob Flash memory. The PLD or other PSD configuration blocks can be programmed through the

JTAG port or a device programmer. Table 6 indicates which programming methods can

program different functional blocks of the PSD.

3.8

Power management unit (PMU)

The power management unit (PMU) gives the user control of the power consumption on

selected functional blocks based on system requirements. The PMU includes an Automatic

Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD unit

has a Power-down mode that helps reduce power consumption.

Doc ID 7833 Rev 7

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