RTL8111C Ver la hoja de datos (PDF) - Realtek Semiconductor
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RTL8111C Datasheet PDF : 47 Pages
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6.9.4.
Bits
31:03
02:00
RTL8111C
Datasheet
PBA Offset/PBA BIR
Table 18. PBA Offset/PBA BIR
RW
Field
Description
RO
PBA Offset Used as an offset from the address contained by one of the function’s Base
Address registers to point to the base of the MSI-X PBA. The lower 3 PBA
BIR bits are masked off (set to zero) by software to form a 32-bit
QWORD-aligned offset.
This field is read only.
RO
PBA BIR
Indicates which one of a function’s Base Address registers, located beginning
at 10h in Configuration Space, is used to map the function’s MSI-X PBA into
Memory Space. The PBA BIR value definitions are identical to those for the
MSI-X Table BIR. This field is read only.
6.9.5.
Bits
31:02
01:00
Message Address for MSI-X Table Entries
Table 19. Message Address for MSI-X Table Entries
RW
Field
Description
RW Message Address System-Specified Message Lower Address.
For MSI-X messages, the contents of this field from an MSI-X Table entry
specifies the lower portion of the DWORD aligned address for the memory
write transaction.
This field is read/write.
RW Message Address For proper DWORD alignment, software must always write zeroes to these
two bits; otherwise the result is undefined.
The state of these bits after reset must be 0.
These bits are permitted to be read only or read/write.
6.9.6.
Bits
31:00
Message Upper Address for MSI-X Table Entries
Table 20. Message Upper Address for MSI-X Table Entries
RW
Field
Description
RW Message Upper Address System-Specified Message Upper Address Bits.
This field is read/write.
6.9.7.
Bits
31:00
Message Data for MSI-X Table Entries
Table 21. Message Data for MSI-X Table Entries
RW
Field
Description
RW
Message Data System-Specified Message Data.
For MSI-X messages, the contents of this field are taken from an MSI-X
Table entry.
In contrast to message data used for MSI messages, the low-order message
data bits in MSI-X messages are not modified by the function.
This field is read/write.
Integrated Gigabit Ethernet Controller for PCI Express
22
Track ID: JATR-1076-21 Rev. 1.5
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