RTL8111C Ver la hoja de datos (PDF) - Realtek Semiconductor
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RTL8111C Datasheet PDF : 47 Pages
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6.8.3.
Bits
31:02
01:00
RTL8111C
Datasheet
Message Address
Table 13. Message Address
RW
Field
Description
RW
Message Address System-Specified Message/Vector Address.
Low DWORD aligned address for MSI memory write transaction.
RO
Reserved
Always Return ‘00’.
This bit is read only.
6.8.4.
Bits
31:00
Message Upper Address
Table 14. Message Upper Address
RW
Field
Description
RW Message Upper Address System-Specified Message/Vector Upper Address.
Upper 32 bits of a 64-bit message/vector address.
This register is effective only when the DAC function is enabled, i.e.,
64-bit addressing is enabled; bit7 in Message Control register is set.
If the contents of this register are 0, the RTL8111C only performs
32-bit addressing for the memory write of the messages/vectors.
This bit is read/write.
6.8.5.
Bits
15:00
Message Data
RW
Field
RW
Message Data
Table 15. Message Data
Description
If the Message Enable bit is set, the message/vector data is driven onto the
lower word of the memory write transaction’s data phase.
This bit is read/write.
Integrated Gigabit Ethernet Controller for PCI Express
19
Track ID: JATR-1076-21 Rev. 1.5
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