MX25L6406E(2010) Ver la hoja de datos (PDF) - Macronix International

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MX25L6406E
(Rev.:2010)

64M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Macronix International 

MX25L6406E

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the

tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the

page is protected by BP3-BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.

(9) Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for

64K-byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)

bit before sending the Block Erase (BE). Any address of the block (see table 1) is a valid address for Block Erase (BE)

instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);

otherwise, the instruction will be rejected and not executed.

The sequence is shown as Figure 19.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the

tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the

page is protected by BP3-BP0 bits, the Block Erase (BE) instruction will not be executed on the page.

(10) Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-

tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the

sector (see table 1) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte

boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-

ecuted.

The sequence is shown as Figure 20.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE

timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip

is protected by BP3-BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when

BP3-BP0 all set to "0".

(11) Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction

must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least sig-

nificant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are

programmed from the start address if the same page (from the address whose 8 least significant address bits (A7-

A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the

byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not

executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request

page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed

at the request address of the page without effect on other address of the same page.

The sequence is shown as Figure 21.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in

P/N: PM1577

REV. 1.1, NOV. 17, 2010

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