MX25L6406E(2010) Ver la hoja de datos (PDF) - Macronix International

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MX25L6406E
(Rev.:2010)

64M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Macronix International 

MX25L6406E

(5) Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on

the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address

is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can

be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been

reached.

The sequence is shown as Figure 15.

(6) Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and

data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at

any location. The address is automatically increased to the next higher address after each byte data is shifted out,

so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when

the highest address has been reached.

The sequence is shown as Figure 16.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-

pact on the Program/Erase/Write Status Register current cycle.

(7) Dual Output Mode (DREAD)

The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising

edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maxi-

mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-

tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-

tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.

The sequence is shown as Figure 17.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

The DREAD only perform read operation. Program/Erase /Read ID/Read status....operation do not support DREAD

throughputs.

(8) Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for

any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit be-

fore sending the Sector Erase (SE). Any address of the sector (see table 1) is a valid address for Sector Erase (SE)

instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);

otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address.

The sequence is shown as Figure 18.

P/N: PM1577

REV. 1.1, NOV. 17, 2010

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