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LH28F016SU

16M (1M × 16, 2M × 8) Flash Memory

Sharp Electronics 

16M (1M × 16, 2M × 8) Flash Memory

LH28F016SU

NOTES:

1. RA can be the GSR address or any BSR address. See Figure 5 and 6 for Extended Status Register Memory Maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Uploaded Status Bits command must be written to reflect the

actual lock-bit status.

3. A0 is automatically complemented to load second byte of data. BY»TE» must be at VIL. A0 value determines which WD/BC is supplied

first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer

contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.

5. In x16 mode, only the lower byte DQ0 - DQ7 is used for WCL and WCH. The upper byte DQ8 - DQ15 is a don’t care.

6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.

7. This command allows the user to swap between available Page Buffers (0 or 1).

8. These commands reconfigure RY »/BY » output to one of two pulse-modes or enable and disable the RY »/BY » function.

9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the

LH28F016SU User’s Manual.

10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.

Compatible Status Register

WSMS

ESS

ES

DWS

VPPS

R

R

R

7

6

5

4

3

2

1

0

CSR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

CSR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase in Progress/Completed

CSR.5 = ERASE STATUS (ES)

1 = Error in Block Erasure

0 = Successful Block Erase

CSR.4 = DATA-WRITE STATUS (DWS)

1 = Error in Data Write

0 = Data Write Successful

CSR.3 = VPP STATUS (VPPS)

1 = VPP Low Detect, Operation Abort

0 = VPP OK

NOTES:

1. RY »/BY » output or WSMS bit must be checked to determine

completion of an operation (Erase Suspend, Erase or Data

Write) before the appropriate Status bit (ESS, ES or DWS)

is checked for success.

2. If DWS and ES are set to ‘1’ during an erase attempt, an

improper command sequence was entered. Clear the CSR

and attempt the operation again.

3. The VPPS bit, unlike an A/D converter, does not provide

continuous indication of VPP level. The WSM interrogates

VPP’s level only after the Data-Write or Erase command

sequences have been entered, and informs the system if

VPP has not been switched on. VPPS is not guaranteed to

report accurate feedback between VPPL and VPPH.

4. CSR.2 - CSR.0 = Reserved for future enhancements.

These bits are reserved for future use and should be

masked out when polling the CSR.

11

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