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LH28F016SC-L

16 M-bit (2 MB x 8) SmartVoltage Flash Memories

Sharp Electronics 

When the set lock-bit operation is complete, status

register bit SR.4 should be checked. If an error is

detected, the status register should be cleared. The

CUI will remain in read status register mode until a

new command is issued.

This two-step sequence of set-up followed by

execution ensures that lock-bits are not accidentally

set. An invalid Set Block or Master Lock-Bit

command will result in status register bits SR.4 and

SR.5 being set to "1". Also, reliable operations

occur only when VCC = VCC2/3/4 and VPP =

VPPH1/2/3. In the absence of this high voltage, lock-

bit contents are protected against alteration.

A successful set block lock-bit operation requires

that the master lock-bit be cleared or, if the master

lock-bit is set, that RP# = VHH. If it is attempted

with the master lock-bit set and RP# = VIH, SR.1

and SR.4 will be set to "1" and the operation will

fail. Set block lock-bit operations while VIH < RP# <

VHH produce spurious results and should not be

attempted. A successful set master lock-bit

operation requires that RP# = VHH. If it is attempted

with RP# = VIH, SR.1 and SR.4 will be set to "1"

and the operation will fail. Set master lock-bit

operations with VIH < RP# < VHH produce spurious

results and should not be attempted.

4.10 Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the

Clear Block Lock-Bits command. With the master

lock-bit not set, block lock-bits can be cleared using

only the Clear Block Lock-Bits command. If the

master lock-bit is set, clearing block lock-bits

requires both the Clear Block Lock-Bits command

and VHH on the RP# pin. See Table 5 for a

summary of hardware and software write protection

options.

Clear block lock-bits operation is executed by a

two-cycle command sequence. A clear block lock-

bits setup is first written. After the command is

LH28F016SC-L/SCH-L

written, the device automatically outputs status

register data when read (see Fig. 8). The CPU can

detect completion of the clear block lock-bits event

by analyzing the RY/BY# pin output or status

register bit SR.7.

When the operation is complete, status register bit

SR.5 should be checked. If a clear block lock-bits

error is detected, the status register should be

cleared. The CUI will remain in read status register

mode until another command is issued.

This two-step sequence of set-up followed by

execution ensures that block lock-bits are not

accidentally cleared. An invalid Clear Block Lock-

Bits command sequence will result in status register

bits SR.4 and SR.5 being set to "1". Also, a reliable

clear block lock-bits operation can only occur when

VCC = VCC2/3/4 and VPP = VPPH1/2/3. If a clear block

lock-bits operation is attempted while VPP ≤ VPPLK,

SR.3 and SR.5 will be set to "1". In the absence of

this high voltage, the block lock-bit contents are

protected against alteration. A successful clear

block lock-bits operation requires that the master

lock-bit is not set or, if the master lock-bit is set,

that RP# = VHH. If it is attempted with the master

lock-bit set and RP# = VIH, SR.1 and SR.5 will be

set to "1" and the operation will fail. A clear block

lock-bits operation with VIH < RP# < VHH produce

spurious results and should not be attempted.

If a clear block lock-bits operation is aborted due to

VPP or VCC transition out of valid range or RP#

active transition, block lock-bit values are left in an

undetermined state. A repeat of clear block lock-bits

is required to initialize block lock-bit contents to

known values. Once the master lock-bit is set, it

cannot be cleared.

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