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LH28F016SC-L

16 M-bit (2 MB x 8) SmartVoltage Flash Memories

Sharp Electronics 

Write Suspend command (see Section 4.8), a byte

write operation can also be suspended. During a

byte write operation with block erase suspended,

status register bit SR.7 will return to “0” and the

RY/BY# output will transition to VOL. However,

SR.6 will remain "1" to indicate block erase

suspend status.

The only other valid commands while block erase is

suspended are Read Status Register and Block

Erase Resume. After a Block Erase Resume

command is written to the flash memory, the WSM

will continue the block erase process. Status

register bits SR.6 and SR.7 will automatically clear

and RY/BY# will return to VOL. After the Erase

Resume command is written, the device

automatically outputs status register data when

read (see Fig. 5). VPP must remain at VPPH1/2/3 (the

same VPP level used for block erase) while block

erase is suspended. RP# must also remain at VIH

or VHH (the same RP# level used for block erase).

Block erase cannot resume until byte write

operations initiated during block erase suspend

have completed.

4.8 Byte Write Suspend Command

The Byte Write Suspend command allows byte

write interruption to read data in other flash memory

locations. Once the byte write process starts,

writing the Byte Write Suspend command requests

that the WSM suspend the byte write sequence at

a predetermined point in the algorithm. The device

continues to output status register data when read

after the Byte Write Suspend command is written.

Polling status register bits SR.7 and SR.2 can

determine when the byte write operation has been

suspended (both will be set to "1"). RY/BY# will

also transition to VOH. Specification tWHRH1 defines

the byte write suspend latency.

At this point, a Read Array command can be

written to read data from locations other than that

which is suspended. The only other valid

LH28F016SC-L/SCH-L

commands while byte write is suspended are Read

Status Register and Byte Write Resume. After Byte

Write Resume command is written to the flash

memory, the WSM will continue the byte write

process. Status register bits SR.2 and SR.7 will

automatically clear and RY/BY# will return to VOL.

After the Byte Write Resume command is written,

the device automatically outputs status register data

when read (see Fig. 6). VPP must remain at

VPPH1/2/3 (the same VPP level used for byte write)

while in byte write suspend mode. RP# must also

remain at VIH or VHH (the same RP# level used for

byte write).

4.9 Set Block and Master Lock-Bit

Commands

A flexible block locking and unlocking scheme is

enabled via a combination of block lock-bits and a

master lock-bit. The block lock-bits gate program

and erase operations while the master lock-bit

gates block-lock bit modification. With the master

lock-bit not set, individual block lock-bits can be set

using the Set Block Lock-Bit command. The Set

Master Lock-Bit command, in conjunction with RP#

= VHH, sets the master lock-bit. After the master

lock-bit is set, subsequent setting of block lock-bits

requires both the Set Block Lock-Bit command and

VHH on the RP# pin. See Table 5 for a summary of

hardware and software write protection options.

Set block lock-bit and master lock-bit are executed

by a two-cycle command sequence. The set block

or master lock-bit setup along with appropriate

block or device address is written followed by either

the set block lock-bit confirm (and an address

within the block to be locked) or the set master

lock-bit confirm (and any device address). The

WSM then controls the set lock-bit algorithm. After

the sequence is written, the device automatically

outputs status register data when read (see Fig. 7).

The CPU can detect the completion of the set lock-

bit event by analyzing the RY/BY# pin output or

status register bit SR.7.

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