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USB3300-EZK-TR

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Microchip Technology 

Chapter 3 Pin Layout

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Datasheet

3.1

The USB3300 is offered in a 32 pin QFN package (5 x 5 x 0.9mm). The pin definitions and locations

are documented below.

USB3300 Pin Diagram

GND 1

GND 2

CPEN 3

VBUS 4

ID 5

VDD3.3 6

DP 7

DM 8

USB3300

HHi-i-SSppeeeeddUUSSBB2

ULPI PHY

32 Pin QFN

GND FLAG

24 DATA0

23 DATA1

22 DATA2

21 DATA3

20 DATA4

19 DATA5

18 DATA6

17 DATA7

3.2

PIN

1

2

3

Figure 3.1 USB3300 Pin Diagram - Top View

The exposed flag of the QFN package must be connected to ground with a via array to the ground

plane. This is the main ground connection for the USB3300.

Pin Function

Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package

NAME

GND

GND

CPEN

DIRECTION, ACTIVE

TYPE

LEVEL DESCRIPTION

Ground

N/A Ground

Ground

N/A Ground

Output,

CMOS

High

External 5 volt supply enable. This pin is used to

enable the external Vbus power supply. The CPEN

pin is low on POR.

SMSC USB3300

11

DATASHEET

Revision 1.1 (01-24-13)

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