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USB3300-EZK-TR

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Microchip Technology 

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Chapter 6 Architecture Overview

Datasheet

The USB3300 architecture can be broken down into the following blocks shown in Figure 6.1,

"Simplified USB3300 Architecture" below.

VDD3.3

Internal

Regulator &

POR

XTAL &

PLL

OTG

Module

VBUS

ID

VDD3.3

DATA[7:0]

CLKOUT

STP

DIR

NXT

ULPI Digital

HS XCVR

Resistors

FS/LS

XCVR

USB3300

Bias

Gen.

Figure 6.1 Simplified USB3300 Architecture

DP

DM

RBIAS

6.1

ULPI Digital

The USB3300 uses the industry standard ULPI digital interface to facilitate communication between

the PHY and Link (device controller). The ULPI interface is designed to reduce the number of pins

required to connect a discrete USB PHY to an ASIC or digital controller. For example, a full UTMI+

Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals.

The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI)

Specification” document (www.ulpi.org). The following sections highlight the key operating modes

of the USB3300 digital interface.

SMSC USB3300

21

DATASHEET

Revision 1.1 (01-24-13)

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