ADM8693ANZ Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADM8693ANZ

Microprocessor Supervisory Circuits

Analog Devices 

ADM8690/ADM8691/ADM8692/ADM8693/ADM8695

In addition to RESET, the ADM8691/ADM8693/ADM8695

contain an active high RESET output. This is the complement of

RESET and is intended for processors requiring an active high

reset signal.

WATCHDOG TIMER RESET

The watchdog timer circuit monitors the activity of the micro-

processor to check that it is not stalled in an indefinite loop. An

output line on the processor is used to toggle the watchdog input

(WDI) line. If this line is not toggled within the selected timeout

period, a RESET pulse is generated. The nominal watchdog

timeout period is preset at 1.6 seconds on the ADM8690 and

ADM8692. The ADM8691/ADM8693/ADM8695 can be

configured for either a fixed short 100 ms, or a long 1.6 second

timeout period, or for an adjustable timeout period. If the short

period is selected, some systems are unable to service the

watchdog timer immediately after a reset, so the ADM8691/

ADM8693/ADM8695 automatically select the long timeout

period directly after a reset is issued. The watchdog timer is

restarted at the end of reset, whether the reset was caused by

lack of activity on WDI or by VCC falling below the reset

threshold.

The normal (short) timeout period becomes effective following

the first transition of WDI after RESET has gone inactive. The

watchdog timeout period restarts with each transition on the

WDI pin. To ensure that the watchdog timer does not time out,

either a high-to-low or low-to-high transition on the WDI pin

must occur at, or less than, the minimum timeout period. If

WDI remains permanently either high or low, reset pulses are

issued after each long (1.6 s) timeout period. The watchdog

monitor can be deactivated by floating the watchdog input

(WDI) or by connecting it to midsupply.

WDI

WDO

t2

t3

RESET

t1

t1

t1

t1 = RESET TIME

t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD

t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET

Figure 16. Watchdog Timeout Period and Reset Active Time

Table 5. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections

Watchdog Timeout Period

Reset Active Period

OSC SEL

OSC IN

Normal

Immediately After Reset ADM8691/ADM8693 ADM8695

Low1

External clock input 1024 CLKs

4096 CLKs

512 CLKs

2048 CLKs

Low1

External capacitor 400 ms × C/47 pF 1.6 s × C/47 pF

200 ms × C/47 pF

520 ms × C/47 pF

Floating or high Low

100 ms

1.6 s

50 ms

200 ms

Floating or high Floating or high

1.6 s

1.6 s

50 ms

200 ms

1 With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal

internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: FOSC (Hz) = 184,000/C (pF).

Rev. B | Page 11 of 20

Share Link: