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74LVC841ABQ Datasheet PDF : 20 Pages
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NXP Semiconductors
74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description
Table 3. Function table[1]
Operating mode
Input
OE
LE
Dn
Enable and read register
L
H
L
(transparent mode)
L
H
H
Latch and read register
L
L
l
L
L
h
Latch register and disable
H
L
l
outputs
H
L
h
Hold
L
L
X
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH to LOW LE transition
Z = high-impedance OFF-state
X = don’t care
NC = no change
7. Limiting values
Internal latches Output
Qn
L
L
H
H
L
L
H
H
L
Z
H
Z
NC
NC
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
VO
output voltage
VI < 0 V
VO > VCC or VO < 0 V
HIGH or LOW state
3-state
0.5
+6.5
V
50
-
mA
[1] 0.5
+6.5
V
-
50
mA
[2] 0.5
VCC + 0.5
V
[2] 0.5
+6.5
V
IO
ICC
IGND
Tstg
Ptot
output current
supply current
ground current
storage temperature
total power dissipation
VO = 0 V to VCC
Tamb = 40 C to +125 C
-
50
mA
-
100
mA
100 -
mA
65
+150
C
[3] -
500
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO24 packages: above 70 C derate linearly with 8 mW/K.
For (T)SSOP24 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN24 packages: above 60 C derate linearly with 4.5 mW/K.
74LVC841A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 2 April 2013
© NXP B.V. 2013. All rights reserved.
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