74LVC841ABQ Ver la hoja de datos (PDF) - NXP Semiconductors.
Número de pieza
componentes Descripción
Fabricante
74LVC841ABQ Datasheet PDF : 20 Pages
| |||
74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs;
3-state
Rev. 4 — 2 April 2013
Product data sheet
1. General description
The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each
latch and 3-state outputs for bus applications. A latch enable (pin LE) input and an output
enable (pin OE) input are common to all internal latches. The device consists of ten
transparent latches with 3-state true outputs. When pin LE is HIGH, data at the Dn inputs
enters the latches. In this condition, the latches are transparent, that is, a latch output
changes each time its corresponding D-input changes. When pin LE is LOW, the latches
store the information that was present at the D-inputs a set-up time preceding the HIGH to
LOW transition of pin LE.
When pin OE is LOW, the contents of the ten latches are available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the pin OE
input does not affect the state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pinout architecture
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C.
Share Link: 