74LVC841ABQ Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LVC841ABQ Datasheet PDF : 20 Pages
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NXP Semiconductors
74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
GND 12
24 VCC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
841
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
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Fig 5. Pin configuration for SO24 and (T)SSOP24
5.2 Pin description
Table 2.
Pin
1
12
13
D[0:9]
Q[0:9]
24
Pin description
Symbol
OE
GND
LE
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
VCC
terminal 1
index area
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
841
GND(1)
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
001aaa837
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration for DHVQFN24
Description
output enable input (active LOW)
ground (0 V)
latch enable input (active LOW)
data input
3-state latch output
supply voltage
74LVC841A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 2 April 2013
© NXP B.V. 2013. All rights reserved.
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